Circuits and Systems II: Express Briefs, IEEE Transactions on (IEEE T CIRCUITS-II)

Publisher: IEEE Circuits and Systems Society; Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers

Current impact factor: 1.23

Impact Factor Rankings

2016 Impact Factor Available summer 2017
2014 / 2015 Impact Factor 1.234
2013 Impact Factor 1.187
2012 Impact Factor 1.327
2011 Impact Factor 1.41
2010 Impact Factor 1.334
2009 Impact Factor 1.32
2008 Impact Factor 1.436
2007 Impact Factor 1.104

Impact factor over time

Impact factor
Year

Additional details

5-year impact 1.55
Cited half-life 7.80
Immediacy index 0.13
Eigenfactor 0.01
Article influence 0.75
Other titles IEEE transactions on circuits and systems. II, Express briefs, Express briefs, Transactions on circuits and systems., Circuits and systems., IEEE transactions on circuits and systems
ISSN 1549-7747
OCLC 54412334
Material type Periodical, Internet resource
Document type Journal / Magazine / Newspaper, Internet Resource

Publisher details

Institute of Electrical and Electronics Engineers

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  • Classification
    green

Publications in this journal


  • No preview · Article · Jan 2016 · Circuits and Systems II: Express Briefs, IEEE Transactions on

  • No preview · Article · Jan 2016 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: An arbitrary waveform generator (AWG) architecture suited for 5G transmission is presented. The digital-to-analog (DA) conversion principle is discussed, underlining its theoretical features toward radio frequency (RF) applications. The signal generation is based on a piecewise linear approximation, resulting from the use of a differential digital coding associated with a custom digital-to-analog converter (DAC), named here the Riemann Pump. The intrinsic performances of this architecture in terms of quantization noise make the Riemann Pump an efficient DAC for multi-carrier applications. Simulations have been carried out on the considered architecture, with a configuration that covers more than 3 GHz bandwidth with a slight oversampling ratio (OSR) and several input bits. Carrier aggregation capabilities are shown with a 5G handset transmission scheme of 10 synchronized 64-QAM modulated signals between 1.8 GHz and 3.6 GHz. This disruptive system exhibits promising performances as for the realization of a 5G handset transmitter with moderate hardware complexity and low power consumption.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: Subband structures are suitable for improving convergence properties of adaptive filtering algorithms, particularly for colored input signals. This brief proposes a new subband adaptive algorithm with sparse adaptive subfilters, which employs the principle of minimal disturbance with multiple-constraint optimization. A performance analysis is carried out, resulting in an expression for the steady-state mean-square error. It is shown that the proposed algorithm, under some particular parameter choices, presents the same performance as that of the normalized subband adaptive filter, but with reduced computational complexity.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: In the High Efficiency Video Coding (HEVC) standard, a notation of the transform unit (TU) is introduced with four different sizes, i.e., 4 $times$ 4, 8 $times$ 8, 16 $times$ 16, and 32 $times$ 32, which results in at least two problems in the use of discrete cosine transform/inversed discrete cosine transform (DCT/IDCT). One is changeable input/output format presented by DCT/IDCT when it deals with TUs of different sizes, which intensifies the nonconformity during the data exchange with other modules. The other is the demand for high throughput to traverse the vast possible TU partitions to find the best one, which would be easily dragged by an inefficient data exchange method. To solve this problem, a parallel-access data mapping method based on single-port static random access memory devices (SRAMs) is proposed in this brief. It can be applied to the data exchange buffers around DCT/IDCT in HEVC encoders to fulfill a high-throughput data exchange. Here, parallel access means one row of 1 $times$ 32 pixels, two rows of 1 $times$ 16 pixels, four rows of 1 $times$ 8 pixels, or four rows of 1 $times$ 4 pixels could be accessed in one cycle depending on the specific size of the current TU.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: A nonvolatile flip-flop (NVFF) is proposed, where magnetic tunnel junctions (MTJs) are incorporated into a CMOS flip-flop (FF) to enable nonvolatility. The voltage-controlled magnetic anisotropy (VCMA) effect is utilized to back up the latched data into MTJs before the power supply is turned off. Switching an MTJ through the VCMA effect does not require a dedicated write circuit for data backup, resulting in reduced area as compared with NVFFs exploiting the spin transfer torque (STT) switching mechanism. In a VCMA-based NVFF, the MTJs are coherently switched, enabling ultra-energy efficient data backup with subnanosecond backup time. Simulation results exhibit more than a 342 $times$ (33.7 $times$) improvement in data backup energy per bit, and more than 35.5 $times$ (7.7 $times$) improvement in data backup delay per bit as compared with the most efficient STT-based NVFFs (spin Hall effect-based NVFF). The energy efficiency of the VCMA-based NVFF results in sufficiently short breakeven times, enabling effective fine-grain power gating.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: This brief relates to communication established through high-speed serial links. A serial communication channel can be formed by grouping multiple high-speed serial communication lanes to achieve greater serial bandwidth. Such channels require circuitry to eliminate relative skew across multiple lanes to ensure data integrity in the receiver. Channel bonding is a mechanism used to synchronize serial communication channels in larger data rate and bandwidth applications. This brief presents an approach to channel bonding that optimizes area, power, and initialization time and yields better performance. The ideas discussed here use a delay-based model and explore the possibility of performing channel bonding in a centralized way. The methodology is deployed in the Aurora Protocol Solution Suite, and a comparative analysis with another state-of-the-art approach is performed.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: In recent years, digital watermarking has facilitated the protection of copyright information through embedding hidden information into the digital content. In this brief, for the first time, a blind multichannel multiplicative color image watermarking scheme in the sparse domain is proposed. In order to take into account the cross correlation between the coefficients of the color bands in the sparse domain, a statistical model based on the multivariate Cauchy distribution is used. The statistical model is then used to derive an efficient closed-form decision rule for the watermark detector. Experimental results and theoretical analysis are presented to validate the proposed watermark detector. The performance of the proposed detector is compared with that of the other detectors. The results demonstrate the improved detection rate and high robustness against the commonly used attacks such as JPEG compression, salt and pepper noise, median filtering, and Gaussian noise.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: Orthogonal frequency-division multiplexing (OFDM) is used in third and fourth generation and is being planned for fifth-generation (5G) systems. OFDM requires that the received subcarriers be orthogonal. However, various factors, such as residual carrier frequency offset due to Doppler shift in mobile fading channels, can lead to a loss in orthogonality between subcarriers, which results in intersymbol interference (ISI), intercarrier interference (ICI), and bit error rate (BER) degradation. In developing the conjugate cancelation (CC) scheme for mitigating these ISI and ICI of OFDM systems, we integrate the CC scheme together with a space-time (ST) system and form an STCC multiple-input-multiple-output (MIMO) scheme. This STCC system improves the BER without expending power or bandwidth or complexity. Additionally, a Walsh-Hadamard (WH) transform is employed as a precoder for this STCC system and forms a novel WHSTCC scheme. It provides a low peak-to-average power ratio (PAPR) at the transmitter and a significant diversity gain at the receiver. Simulations indicate that both STCC and WHSTCC schemes outperform the regular CC and ST systems in mobile fading channels. Both schemes are simple and are backward compatible, and they can serve as the baseband building block for reconfigurable 5G multiuser MIMO systems.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: Due to the structural coupling of a space shuttle vehicle, the selection of a suitable controller gain has been a difficult task. However, this task is very critical as it will affect the performance of the controller. In this brief, a band-stop filter is constructed by using a combined network of a low-pass filter and a high-pass filter. On this basis, digital processing is carried out using bilinear transformation and predistorted processing. To solve the parameters of the filter, a frequency-domain method and an optimization method are applied. The designed filter can effectively reduce the structural coupling, as well as broaden the margin for the regulation of the control law.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: A new all-digital impulse radio ultrawideband pulse generator in a 65-nm CMOS technology for a wireless body area network is presented. The system architecture is a delay-based pulse generator that is designed using only logic gates to minimize the power consumption. The system uses a frequency range of 3.1–4.8 GHz and 3 channels with a 500-MHz bandwidth. The maximum data rate of this system is 100 Mb/s with pulse positioned modulation and 200 Mb/s with on–off keying. Delay-based binary phase-shift keying is used to achieve an efficient spectral line characteristic. The total power consumption of the pulse generator is 30 pJ/pulse at a 1.2-V supply voltage without a static bias current.
    No preview · Article · Dec 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: This brief presents a new parallel architecture for linear feedback shift registers (LFSRs), which can be used to achieve high-throughput Bose-Chaudhuri-Hocquenghem or cyclic redundancy check encoders for storage and communication systems. While previous parallel LFSR architectures have computed values by using the past input messages and the register outputs, the proposed parallel architecture based on the transposed serial LFSR calculates the output by using only the past feedback values. As a result, the proposed architecture reduces the area-time product by up to 59% compared with the recent architecture.
    No preview · Article · Nov 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on
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    ABSTRACT: A subharmonically injection-locked all-digital phase-locked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without a time-to-digital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process; it consumes 3.04 mW under a standard supply of 1.1 V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4 dBc/Hz at 1-MHz offset. The integrated RMS jitter is 109.6 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure-of-merit is equal to -254.39 dB.
    No preview · Article · Nov 2015 · Circuits and Systems II: Express Briefs, IEEE Transactions on