IEEE International Test Conference (TC)

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ISSN 1089-3539

Publications in this journal

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    ABSTRACT: Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.
    No preview · Article · Sep 2013 · IEEE International Test Conference (TC)
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    ABSTRACT: Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: In this summary paper, we discuss two types of sensors that provide a built-in test solution for RF circuits. The key characteristic of the sensors is that they are non-intrusive, in the sense that they are not electrically connected to the RF circuit under test. This has the important advantage that the design of the RF circuit becomes totally independent from the design of the sensors. In other words, the RF circuit design methodology and performance trade-offs are totally transparent to the insertion of the built-in test strategy. In particular, we propose variation-aware sensors to implement an implicit functional test and a temperature sensor to implement a defect-oriented test. The proposed sensors provide DC or low-frequency measurements, thus they have the potential to reduce drastically the test cost. We discuss the principle of operation of the sensors, we provide design guidelines, and we demonstrate the concept on a set of fabricated chips. To the best of our knowledge, this is the first proof-of-concept of RF test based on non-intrusive sensors.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: This paper describes our deployment of data mining techniques during final test to predict system level test failures and customer returns for two recent mixed-signal system-on-chip products. Emphasis is put on practical considerations for simplifying test flow implementation while still meeting the twin goals of reduced test cost and improved product quality.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad scan chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) scan chain stitching method, which is pattern independent and supports embedded scan compaction. It is based on three ideas: (1) increasing the number of sensitive scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive scan cells along the scan chains to enhance the overall resolution; (3) stitching scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA scan chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item correlations in the test data for test time and cost reduction. We first describe a statistical regression method, called group lasso, which can identify inter-test-item correlations from test data. After learning such correlations, some test items can be identified for removal from the test program without compromising test quality. An extended version of this method, weighted group lasso, allows taking into account the distinct test time/cost of each individual test item in the formulation as a weighted optimization problem. As a result, its solution would favor more costly test items for removal from the test program. We further integrate weighted group lasso with another statistical regression technique, virtual probe, which can learn spatial correlations of test data across a wafer. The integrated method could then utilize both spatial and inter-test-item correlations to maximize the number of test items whose values can be predicted without measurement. Experimental results of a high-volume industrial device show that utilizing both spatial and inter-test-item correlations can help reduce test time by up to 55%.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite these advances, it is often the case however that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. Imperfect resolution greatly hinders any follow-on, information-extraction analyses (e.g., physical failure analysis, volume diagnosis, etc.) due to the resulting ambiguity. To address this major challenge, a novel, unsupervised learning methodology that uses ordinarily-available tester and simulation data is described that significantly improves resolution with virtually no negative impact on accuracy. Simulation experiments using a variety of fault types (SSL, MSL, bridges, opens and cell-level input-pattern faults) reveal that the number of failed ICs that have perfect resolution can be more than doubled, and overall resolution is improved by 22%. Application to silicon data also demonstrates significant improvement in resolution (38% overall and the number of chips with ideal resolution is nearly tripled) and verification using PFA demonstrates that accuracy is maintained.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: SNR enhancement of a 6-band WCDMA/ HSDPA+ directconversion transceiver supporting 21 Mbps High Speed Downlink Packet Access Evolved (HSDPA+) in a single CMOS die is evaluated in this paper. The paper mainly focuses on enhancing SNR performance of a WCDMA/HSDPA+ receiver by minimizing the error vector magnitude (EVM) with the digital compensations of the amplitude and group delay variations of the analog channel selection filter, and bandwidth optimization in the cases of the absence and presence of the adjacent channel interferers (ACIs). The measurement results show that the receiver achieves RX EVM below 3% and 4%, respectively, for WCDMA QPSK and HSDPA+ 64-QAM signals across a very wide input signal power range in all bands, and negligible SNR degradation in the presence of the ACIs.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians' knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, we propose a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests. Experimental results on a real industrial board and an OpenRISC design demonstrate the effectiveness of the proposed solution.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: form only given. Intel architecture scales from Exa-scale computing to hand-held and deeply embedded devices. A consistent architecture spanning many product domains brings benefits to silicon and product developers. But it also creates a validation challenge that is nonlinear in nature due to the differences in product complexity, use cases, and user expectations. In this talk, John will address how Intel views the reliability/resilience of large scale systems, how we test for user experience that might help users decide what is good for them, how we attempt to balance all the conflicting validation requirements in today's rapidly evolving landscape spanning consumption devices with short life spans to enterprise applications with very high uptime and reliability expectations. In addition, he will comment on the developments in formal methods and their applicability to large-scale commercial validation/verification efforts.
    Preview · Conference Paper · Sep 2013
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    ABSTRACT: For spectral testing of Built-in Self-Test Analog to Digital Converters, it is a very challenging task to precisely control the amplitude and frequency of input sinusoid signal. Amplitude over-range results in clipping ADC output and non-coherent sampling results in spectral leakage. In this paper, a new method is proposed that provides accurate spectral results even when the input to ADC is both over-ranged and non-coherently sampled. This relaxes the condition to have precise control over the input signal and thus decreases the cost. The method includes fundamental identification, removal and residue interpolation to obtain accurate spectral results. Simulations show the functionality and robustness of proposed method with both non-coherency and amplitude over-range. Measurement results of a commercially available 16-bit SAR ADC are used to verify the method for both functionality and robustness.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs. Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability. Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely. In this paper, we present an automatic test pattern generation (ATPG) technique based on Boolean Satisfiability (SAT) for detecting ELF-induced delay changes at all gates in a given circuit. Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection. We also demonstrate the robustness of our approach to manufacturing process variations.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: Three-dimensional (3D) stacking of ICs using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a pre-bond stage. In order to increase testability, it has been advocated that wrapper cells be added at both ends of a TSV. However, a drawback of wrapper cells is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of wrapper cells that need to be inserted; however, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. We show that the general problem of minimizing the wrapper cells is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layout-aware solution. We also evaluate the heuristic methods using an exact solution technique based on integer linear programming. Results are presented for 3D-stack implementations of the ITC'99 and the OpenCore benchmark circuits.
    No preview · Conference Paper · Sep 2013
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    ABSTRACT: In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.
    No preview · Conference Paper · Jan 2013
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    ABSTRACT: Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new procedure has a higher accuracy and a broader coverage.
    No preview · Conference Paper · Jan 2013