Proceedings of the International Workshop on Rapid System Prototyping

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ISSN 1074-6005

Publications in this journal

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    ABSTRACT: This paper presents a distributed hardware/software cosimulation environment for heterogeneous systems prototyping applied to an industrial application. The environment provides following features: distributed Hw/Sw cosimulation, automatic Hw/Sw interface generation, Hw elements can be described at different levels of abstraction and generic/specific Sw debuggers can be used. Starting from a brief description of the interface of the interconnected modules the tool automatically produces the link between Hw and Sw parts. In addition, the environment is very easy to use, even for complex systems that may include several Sw (C) modules and several Hw (VHDL) modules running in parallel. Applied to a large industrial multi-processor system, this method appeared reliable and efficient, providing important benefits in hardware-software codesign: better design environment and reduced time to validate.
    No preview · Article · Feb 2013 · Proceedings of the International Workshop on Rapid System Prototyping
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    ABSTRACT: Synthesis and Characterisation of hydrophobic polymer, for depollution of contaminated water by inorganic and organic chemicals
    No preview · Article · Jan 2012 · Proceedings of the International Workshop on Rapid System Prototyping
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    ABSTRACT: In order to address the large variety of channel coding options specified in existing and future digital communi- cation standards, there is an increasing need for flexible solutions. Recently proposed flexible solutions in this context generally presents a significant area overhead and/or throughput reduction compared to dedicated implementations. This is particularly true while adopting an instruction-set programmable processors, including the recent trend toward the use of Application Specific Instruction-set Processors (ASIP). In this paper we illustrate how the application of adequate algorithmic and architecture level optimization techniques on an ASIP for turbo decoding can make it even an attractive and efficient solution in terms of area and throughput. The proposed architecture integrates two ASIP com- ponents supporting binary/duo-binary turbo codes and combines several optimization techniques regarding pipeline structure, trellis compression (Radix4), and memory organization. The logic synthesis results yield an overall area of 1.5mm 2 using 90nm CMOS technology. Payload throughputs of up to 115.5Mbps in both double binary Turbo codes (DBTC) and single binary (SBTC) are achievable at 520MHz. The demonstrated results constitute a promising trade-off solution between throughput and occupied area comparing with existing implementations.
    No preview · Conference Paper · May 2011
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    ABSTRACT: It is well known that validation and verification is the most time consuming step in complex System-on-Chip design. Thus, different validation and verification approaches and methodologies for various implementation styles have been de- vised and adopted by the industry. Application specific instruction set-processors (ASIPs) are an emerging implementation technol- ogy to solve the energy efficiency/flexibility trade-off in baseband processing for wireless communication where multiple standards have to be supported at a very low power budget and a small silicon footprint. In order to balance these contrary aims ASIPs for these application domains have a restricted functionality tailored to a specific class of algorithms compared to traditional ASIPs. Downside of the outstanding efficiency/flexibility ratio is the coincidence of bad attributes for validation. Compared to standard processors, these ASIPs often have a very complex instruction set architecture (ISA) due to the tight coupling between the instructions and the optimized micro-architecture requiring new validation concepts. This paper will sensitize for the distinctiveness and complexity of the validation of ASIPs tailored to channel decoding. In a case study a composite approach comprising formal methods as well as simulations and rapid-prototyping for validating an existing channel decoding ASIP is applied and transferred it into an industry product.
    No preview · Conference Paper · May 2011
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    ABSTRACT: Model-Driven Engineering (MDE) based approaches have been proposed as a solution to cope with the inefficiency of current design methods. In this context, this paper presents an MDE-based framework for rapid SIMD (Single Instruction Mul- tiple Data) parametric parallel SoC (System-on-Chip) prototyp- ing to deal with the ever-growing complexity of such embedded systems design process. The design flow covers the design phases from system-level modeling to FPGA prototyping. The proposed framework allows the designer to easily and automatically gener- ate a VHDL parallel SoC configuration from a high-level system specification model using the MARTE (Modeling and Analysis of Real-Time and Embedded systems) standard profile. It is based on an IP (Intellectual Property) library and a basic parallel SoC model. The generated parallel configuration can be adapted to the data-parallel application requirements. In an experimental setting, four steps are needed to generate a parallel SoC: data- parallel programming, SoC modeling, deployment and generation process. Experimental results for a video application validate the approach and demonstrate that the proposed framework facilitates the parallel SoC exploration.
    No preview · Conference Paper · May 2011
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    ABSTRACT: Classic MPSoCs tend to be fully implemented using a single communication approach. However, recent efforts have shown a new promising multiprocessor system-on-chip infrastructure: cluster-based or clustered MPSoC. This infrastructure adopts hybrid interconnection schemes where both buses and NoCs are used in a concomitant way. The main idea is to decrease the size and complexity of the NoC by using bus based communication systems at each local port. For example, while in a classic approach a 16 processor NoC might be formed in a 4 x 4 arrangement, in cluster-based MPSoCs a 2 x 2 NoC is employed and each router connected to a local port contains buses that carry 4 processors. Nevertheless, although good results have been reached using this approach, the implementation of wrappers to connect the local router port to the bus can be complex. Therefore, we propose in this work the use of embedded virtualization, another current promising technique, to achieve similar results to cluster based MPSoCs without the need for wrappers besides providing a decreased area usage.
    No preview · Conference Paper · May 2011
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    ABSTRACT: Instrumentation methods for code profiling, tracing and semihosting on virtual platforms (VP) and instruction-set simulators (ISS) rely on function call and system call interception. To reduce instrumentation overhead that can affect program behavior and timing, we propose a novel low-overhead flexible instrumentation framework called Virtual Platform Instrumentation (VPI). The VPI framework uses a new table-based parameter-passing method that reduces the runtime overhead of instrumentation to only that of the interception. Furthermore, it provides a high-level interface to extend the functionality of any VP or ISS with debugging support, without changes to their source code. Our framework unifies the implementation of tracing, profiling and semihosting use cases, while at the same time reducing detrimental runtime overhead on the target as much as 90 % compared to widely deployed traditional methods, without significant simulation time penalty. Index Terms—Computer simulation, Software debugging, Software prototyping, System-level design
    No preview · Conference Paper · Jan 2011
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    ABSTRACT: Multiprocessor systems-on-chips (MPSoCs) are defined as one of the main drivers of the industrial semiconductors revolution. They are good candidates for systems and applications such as multimedia. Memory is becoming a key player for significant improvements in these applications (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. The large amount of data manipulated by these applications requires high-capacity calculation and memory. This leads to the need of new optimization and mapping techniques. This paper presents a novel approach for combining memory optimization with mapping of data-driven applications. This approach consists of task graph transformation and its integration to existing mapping algorithms. Some significant improvements are obtained for memory gain, communication load and physical links.
    No preview · Conference Paper · Jun 2010
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    ABSTRACT: In embedded system design, the tuning and validation of a cycle accurate simulator is a difficult task. The designer has to assure that the estimation error of the simulator meets the design constraints on every application. If an application is not correctly estimated, the designer has to identify on which parts of the application the simulator introduces an estimation error and consequently fix the simulator. However, detecting which are the mispredicted parts of a very large application can be a difficult process which requires a lot of time. In this paper we propose a methodology which helps the designer to fast and automatically isolate the portions of the application mispredicted by a simulator. This is accomplished by recursively analyzing the application source code trace highlighting the mispredicted sections of source code. The results obtained applying the methodology to the TSIM simulator show how our methodology is able to fast analyze large applications isolating small portions of mispredicted code.
    No preview · Conference Paper · Jun 2010
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    ABSTRACT: The TrueTime toolbox simulates real-time control systems, including platform-specific details like process scheduling, task execution and network communications. Analysis using these models provides insight into platform-induced timing effects, such as jitter and delay. For safety-critical applications, the Time-Triggered Architecture (TTA) has been shown to provide the necessary services to create robust, fault-tolerant control systems. Communication induced timing effects still need to be simulated and analyzed even for TTA-compliant models. The process of adapting time-invariant control system models, through the inclusion of platform specifics, into TTA-based TrueTime models requires significant manual effort and detailed knowledge of the desired platform's execution semantics. In this paper, we present an extension of the Embedded Systems Modeling Language (ESMoL) tool chain that automatically synthesizes TTA-based TrueTime models. In our tools, timeinvariant Simulink models are imported into the ESMoL modeling environment where they are annotated with details of the desired deployment platforms. A constraint-based offline scheduler then generates the static TTA execution schedules. Finally, we synthesize new TrueTime models that encapsulate all of the TTA execution semantics. Using this approach it is possible to rapidly prototype, evaluate, and modify controller designs and their hardware platforms to better understand deployment induced performance and timing effects.
    No preview · Conference Paper · Jan 2010
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    ABSTRACT: With increased complexity of software systems being developed; analysis of use case scenarios is gaining importance leading to effective test case identification during early part of the life cycle. Existing approaches provide various methods for analysis of UML activity diagrams and scenario path identification based on graph models of activity diagrams. In most cases these methods consider a single activity diagram. However use case scenarios may span multiple activity diagrams, which have become quite common with distributed development of software systems. In this paper we propose Activity Relationship graph model that depicts the interrelationship of activity diagrams modeling a use case. Activity Relationship graph ARG is a hierarchical graph where each node depicts an activity diagram modeled as activity diagram graph (AG). We also define a set of metrics named Use case Scenario Paths (USP) that measures the minimum number of independent paths in ARG. An algorithm is proposed to analyze ARG and derive the number of Use case Scenario Paths. This gives a measure of the number of test paths for a requirement based on analysis models early in the life cycle.
    No preview · Conference Paper · Jan 2010