Proceedings of the Custom Integrated Circuits Conference

Publisher: Institute of Electrical and Electronics Engineers

Current impact factor: 0.00

Impact Factor Rankings

Additional details

5-year impact 0.00
Cited half-life 0.00
Immediacy index 0.00
Eigenfactor 0.00
Article influence 0.00
ISSN 0886-5930

Publisher details

Institute of Electrical and Electronics Engineers

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Author's pre-print on Author's personal website, employers website or publicly accessible server
    • Author's post-print on Author's server or Institutional server
    • Author's pre-print must be removed upon publication of final version and replaced with either full citation to IEEE work with a Digital Object Identifier or link to article abstract in IEEE Xplore or replaced with Authors post-print
    • Author's pre-print must be accompanied with set-phrase, once submitted to IEEE for publication ("This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible")
    • Author's pre-print must be accompanied with set-phrase, when accepted by IEEE for publication ("(c) 20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.")
    • IEEE must be informed as to the electronic address of the pre-print
    • If funding rules apply authors may post Author's post-print version in funder's designated repository
    • Author's Post-print - Publisher copyright and source must be acknowledged with citation (see above set statement)
    • Author's Post-print - Must link to publisher version with DOI
    • Publisher's version/PDF cannot be used
    • Publisher copyright and source must be acknowledged
  • Classification
    green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: This work presents an ultra-low power oscillator designed for wake-up timers in compact wireless sensors. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18μm CMOS, the oscillator consumes 5.8nW at room temperature with temperature stability of 45ppm/°C (-10°C to 90°C) and 1%V line sensitivity.
    No preview · Conference Paper · Sep 2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: This article describes 40V N-channel MESFETs fabricated at a commercial 32nm SOI CMOS foundry without changing any of the process flow or including additional mask steps. The 32nm technology node is the most advanced technology node to date for MESFET fabrication and builds upon previous work completed at other process nodes. High voltage MESFETs were measured with current drives of 110mA/mm. The devices are suitable for RF development and have peak cut-off frequency, fT, of 30.5GHz and maximum oscillation frequency, fmax, of 34.5GHz.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A voltage mode transmitter employs pulse width modulation (PWM) based equalization of NRZ input data at 5 Gb/s and compensates 28 dB channel loss at 2.5 GHz. Fabricated in a 90 nm CMOS process, the proposed transmitter achieves a horizontal eye opening of 0.3UI with BER
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a tunable transmission line (t-line) structure, featuring independent control of line inductance and capacitance. The t-line provides variable delay while maintaining relatively constant characteristic impedance using direct digital control through FET switches. As an application of this original structure, a 60 GHz RF-phase shifter for phased-array applications is implemented in a 32 nm SOI process attaining state-of-the-art performance. Measured data from two phase shifter variants at 60 GHz showed phase changes of 175° and 185°, S21 losses of 3.5-7.1 dB and 6.1-7.6 dB, RMS phase errors of 2° and 3.2°, and areas of 0.073 mm2 and 0.099 mm2 respectively.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Discrete-time charge-steering circuits consume less power than their continuous-time current-steering counterparts even at high speeds. This advantage can be exploited in the design of semi-analog circuits such as latches, demultiplexers, and CDR circuits as well as mixed-mode systems such as ADCs. Employing charge steering in 65-nm CMOS technology, a 25-Gb/s CDR/deserializer consumes 5 mW and a 10-bit 800-MHz pipelined ADC draws 19 mW.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper reports the first 8kV+ ESD-protected SP10T transmit/receive (T/R) antenna switch for quad-band (0.85/0.9/1.8/1.9-GHz) GSM and multiple W-CDMA smartphones fabricated in an 180-nm SOI CMOS. A novel physics-based switch-ESD co-design methodology is applied to ensure full-chip optimization for a SP10T test chip and its ESD protection circuit simultaneously.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an entire receiver chain from RF to baseband with fully integrated self-calibration circuitries for suppressing the 2nd-order intermodulation (IM2) distortions in Homodyne receivers for multi-standard applications. All the potential sources for IM2 generation are identified and tackled independently in the proposed receiver by architectural and calibration techniques, which results in a very robust IP2 enhancement with independency of the amplitude and the frequency of the blockers. The prototype receiver implemented in a 90 nm CMOS process achieves at least 10 dB improvement on the receiver IP2 performance at high-power blockers and less than 100 μs calibration cycle for whole receiver chain. It potentially provides truly SAW-Less, fully integrated, and frequency-agile receivers.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal with the received signal. The circuit is fabricated in 90-nm CMOS and can be configured to work from 50Mb/s to 1Gb/s with Barker codes. A sidelobe reduction (SLR) of 15.6dB is demonstrated for 1Gb/s. The total power consumption is 33mW at 1Gb/s.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: We introduce a stochastic time-to-digital converter (TDC) that has 180-770fs tunable resolution, less than 0.6LSB INL, and selectable dynamic range offset. Previous arbiter-based TDCs have fine resolution but small dynamic range which is difficult to calibrate. Our approach uses comparators as decision elements to precisely control dynamic range offset.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a frequency-shaping (FS) neural recording interface that can inherently reject electrode offset, 5-10 times increase input impedance, 4.5-bit extend system dynamic range (DR), and provide much more tolerance to motion artifacts and 50/60 Hz power noise interferences. It is supposed to be more suitable for long-term brain-machine-interface (BMI) experiments. To achieve the mentioned performance above, the proposed architecture adopts an auto-zero offset calibration to avoid system saturation, a delayed-signaling noise cancellation to attenuate kT/C noise, and an automatical data-splitting technique to reduce input-referred noise at low frequencies. Measured at a 40 kHz sampling clock and ± 0.6 V supply, the recorder consumes 50 μW/ch, including 22 μW for FS amplifier, 12 μW for gain-stage amplifier, 12 μW for buffer, and 4 μW for successive approximation register (SAR) analog-to-digital converter (ADC). The designed SAR ADC achieves an effective-number-of-bit (ENOB) of 11-bit in a 160 kHz bandwidth. In addition, the recorder has a 3 pF input capacitance and 15.5-bit (11-bit+4.5-bit) system DR due to the utilization of FS technique. The designed chip occupies 0.76 mm2/ch in a 0.13 μm CMOS process.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: As modern electrical and optical communication systems transition toward advanced modulation schemes, there exists a pressing need for power efficient A/D converters operating at tens of gigasamples per second. Within this context, this tutorial will cover relevant circuit-and architecture-level design techniques for high-speed CMOS A/D converters. At the circuit level, we will discuss fundamental challenges in the design of track-and-hold circuits and voltage comparators, which will also include a review of clock jitter and metastability. At the architecture level, we consider tradeoffs in the design of time-interleaved SAR and flash converters as well as techniques for the estimation, system-level budgeting and calibration of circuit imperfections.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper analyzes cause of deviation from Pelgrom scaling law in threshold voltage (Vth) variability of pocket-implanted long channel MOSFET. It has been reported that this deviation from Pelgrom scaling law becomes remarkable in 65nm and beyond technologies. It is clarified that deviation from Pelgrom scaling law is attributed to increasing behavior of offset-voltage variability σ(ΔI/gm) in weak and moderate inversion regions. It is found that this increasing behavior of σ(ΔI/gm) can be completely eliminated by using both-side (BS) ring gate structure. This means that deviation from Pelgrom scaling law is caused by subthreshold hump.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: The multigate nanowire FET architecture allows for ultimate short-channel control and push Moore's law down to sub-5nm gate lengths. This paper reviews nanowire transistor device physics as well as circuit prospects in the fields of CMOS logic, memory, analog, RF and integrated sensor applications.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: An 11b asynchronous successive approximation register analog to digital converter with embedded passive gain architecture is proposed and prototyped in 65nm CMOS. The proposed passive gain technique is integrated in the sampling capacitor network as part of the SAR conversion, and provides a signal gain of 2x prior to the comparator without consuming static current. It thus reduces the comparator noise impact as well as enhancing the overall ADC conversion speed and power efficiency. The ADC prototype demonstrates a peak SNDR of 63.1dB and SFDR of 75.2dB when sampling at 95MS/s. Both measured differential and integral nonlinearities of the prototype are less than 0.84 LSB. It occupies an active area of 0.073mm2 and dissipates 1.36mW from 1.1V supply.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 5th order continuous time delta sigma modulator is designed in 0.18μm CMOS. At a sampling rate of 500MHz it achieves 76dB SNDR over a 10MHz bandwidth consuming 58mW. 5th order noiseshaping is realized with 4 opamp based RC integrators and a VCO realizing an integrator and a 4 bit quantizer. A THD of -82.3dBc is achieved without calibration of feedback DACs. A high speed capacitive implementation of excess loop delay compensation, together with a method for reducing the switching activity of the output codes from the VCO are proposed.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we present a novel switched-capacitor filter based Type-III compensation architecture for closed-loop regulation of fixed-frequency switched-mode Buck converters. Compared to the conventional all-analog filter, the proposed compensator can be fully-integrated onto the die resulting in reduced footprint and cost. In addition, the filter time constants scale linearly with the Buck converter's switching time-period, resulting in increased programmability and ease-of-use. A prototype of a voltage-mode PWM controller with programmable Buck Converter switching frequencies of 0.5 and 1 MHz, has been implemented and validated in a 0.36-μm BCD process, consumes 1.1 mA of static current from a 3.3 V supply, and occupies ~ 0.65 mm2 of active area on-chip.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A high-sensitivity, high dynamic range photodetection sensor front-end is presented, suitable for low-cost hand-held food safety systems. This sensor front-end for detecting organophosphorus (OP) compounds incorporates an on-chip deep N-well photodetector, pulse width modulation (PWM), and a folded reference. Designed in a 0.18 μm process, measurement results show an input optical power dynamic range of 71 dB, a sensitivity of 3.6nW/cm2 (0.77pA), and a power consumption of 14.5 μW. OP compound detection experiments demonstrate a limit of detection (LOD) of 0.16u mol/L, comparable to that of a commercial spectrophotometer.
    No preview · Conference Paper · Nov 2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 4-bit 65nm time-based analog-to-digital converter (ADC) targeting the next-generation Square Kilometre Array (SKA) is presented. This ADC is composed of an analog voltage-to-time converter (VTC) front end and a digital time-to-digital converter (TDC) back end. The two components can be physically separated to minimize the impact of digital noise from the ADC on high-gain, high-sensitivity receiver chains common in radio telescopes. At a sampling rate of 5 GS/s the ADC consumes 35 mW from a 1 V supply. After calibration, the ADC achieves a peak SNDR of 22.9 dB, SFDR of 34.0 dB and ENOB of 3.5. At the ERBW of 2100 MHz, SNDR is 18.4 dB, SFDR is 22.3 dB and ENOB is 2.8. The resulting worst-case figure of merit is 1.0 pJ/conversion. This is the highest reported sampling rate for a time-based ADC to date.
    No preview · Conference Paper · Nov 2013