Proceedings of The International Symposium on Multiple-Valued Logic

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ISSN 0195-623X

Publications in this journal

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    ABSTRACT: We give single-operations characterizations for submodular and supermodular functions on lattices that have monotonicity properties. We associate to such functions metrics on lattices and we investigate corresponding metrics on the sets of partitions.
    No preview · Conference Paper · May 2014
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    ABSTRACT: In this paper, a delay-variation effect under alpha-particle strikes is evaluated in content-addressable memories (CAMs). The particle strikes into transistors induce a current-pulse signal that causes the delay variation, resulting in a timing error, called a soft-delay error (SDE). The delay variations in two different CAMs designed in a 90nm CMOS technology are simulated in NS-SPICE using a charge-injection model that generates a current-pulse signal. The SDE effects are discussed, where one of the CAMs is a traditional 9-transistor-cell CAM and the other one is a magnetic-tunnel-junction (MTJ)/MOS hybrid CAM that operates based on a multiple-valued current-mode logic. The simulation results show that there is a trade-off between the amount of current (thus power dissipation) and the SDE effects in the MTJ/MOS hybrid CAM.
    No preview · Conference Paper · May 2014
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    ABSTRACT: This paper presents an efficient approach to verifying higher-degree Galois-Field(GF) arithmetic circuits. The proposed method describes GF arithmetic circuits by graph-based representation, and verifies them by a combination of algebraic method with a new verification method based on natural deduction for the first-order predicate logic with equal sign. The natural deduction method can verify kind of higher-degree GF arithmetic circuits efficiently while the conventional methods requires enormous time to verify them or sometimes cannot verify them. In this paper, we apply the proposed method to the design and verifications of various Reed-Solomon (RS) code decoders. We confirm that the proposed method can verify RS code decoders with higher-degree functions while the conventional method fails. In particular, we show that the proposed method can be applied to practical decoders with 8-bit symbols.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Varieties of commutative residuated lattices are algebraic counterparts of extensions of the substructural logic FLe. We present four new construction methods that result in involutive commutative residuated monoids, namely, connected co-rotation, connected and disconnected co-rotation-annihilation, and the involutive ordinal sums construction. All constructions are suitable for constructing nonpositive rank FLe-algebras. The last one is suitable for constructing new zero-rank (that is, group-like) FLe-algebras from a family of such algebras.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Reliability analysis of Multi-State System is one of fields, where the methods of the multiple-valued logic are used efficiently. Multi-State System is a mathematical model in reliability engineering, which allows considering some performance level in the system reliability behavior. The principal problem in the reliability engineering is identification of the system components that have the most influence on the system reliability. One of possible approaches, which can be used for this task, is to identify minimal cut sets (or minimal cut vectors (MCVs)). MCVs represent situations in which the repair of any damaged component causes the system improvement. In this paper, the new theoretical background for identification of MCVs is considered. The presented method is based on logical differential calculus.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Any matrix of the unitary group U(n) can (up to a global phase) be decomposed into 2n-1 matrices from two subgroups, denoted XU(n) and ZU(n). This leads to the decomposition of an arbitrary quantum circuit into NEGATOR circuits and PHASOR circuits. The NEGATOR circuits are closely related to classical reversible computation.
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    ABSTRACT: In this paper, we deal with two kinds of uncertainties in distributed systems. On one hand, the order of causally unrelated executions is not determined when a global clock is not available. On the other hand, in a finite amount of time, the behaviour can be observed only up to a certain moment, and the future behaviour is unknown. In this paper, we investigate a monitoring approach based on linear temporal logic (LTL) specifications. We propose a five-valued semantics for LTL to deal with both kinds of uncertainties. We develop an efficient runtime verification algorithm using formula rewriting, and show the feasibility of our approach with a case study in the railway domain.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Nonvolatile multiple-valued programmable resistors based on series-parallel-connected magnetic tunnel junction (MTJ) devices are proposed for process-variation-resilient logic LSIs. Since the proposed resistors are designed using several MTJ devices of equal size, they can be fabricated without using special fabrication technologies such as that used to fabricate conventional MTJ-based multilevel resistors. In this paper, the process variation tolerance of the proposed resistors is evaluated through the Monte-Carlo analysis using a SPICE simulator with built-in MTJ device model.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Two well-studied closure operators for relations are based on primitive positive (p.p.) definitions and quantifier free p.p. definitions. The latter do however have limited expressiveness and the corresponding lattice of strong partial clones is uncountable. We consider implementations allowing polynomially many existentially quantified variables and obtain a dichotomy for co-clones where such implementations are enough to implement any relation and prove (1) that all remaining co-clones contain relations requiring a superpolynomial amount of quantified variables and (2) that the strong partial clones corresponding to two of these co-clones are of infinite order whenever the set of invariant relations can be finitely generated.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Reversible logic is being studied extensively due to its applications in the design of nanoscale circuits with ultra-low power dissipation and future technologies such as quantum computing. Most methods that synthesize reversible logic circuits are restricted to small functions and are thus, not scalable. Previous methods based on Binary Decision Diagrams (BDD) are scalable but introduce a large number of additional circuit lines. In this paper, we present a technique that maps subgraphs of the BDD to structures with known reversible-circuit templates by posing this as a subgraph isomorphism problem. Experimental results show that this approach reduces the number of additional circuit lines introduced by previous approaches while retaining their scalability. We further show that for small functions, there is also an improvement in the quantum cost.
    No preview · Conference Paper · May 2014
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    ABSTRACT: After presenting a very general framework of set approximation the author shows that it can be the set-theoretical base of the semantics of a partial three-valued first-order logic. Approximative functors can appear in object language, and so the properties of set approximation can be given as logical laws. Permitting semantic partiality gives a possibility to make correct difference between the following different cases: a predicate is true, false, uncertain or undefined for an object. Some important laws are proved in order to show the characteristic behavior of introduced logical system. They open doors before the investigation of different consequence relations in order to show how one can make a valid inference relying on represented and not total knowledge. Partiality appears in many information systems, and so the theoretical results can be applied in practice in the future.
    No preview · Conference Paper · May 2014
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    ABSTRACT: In this paper we consider S-threshold functions defined on not necessarily binary input. By S-threshold function, in an arbitrary dimension we mean a function which can be written as a linear combination of monomials from a predefined set. First, we determine sets of discrete moments which uniquely determine such functions. Based on these, we derive a generic formula for the upper bound of the functions considered. The formula is generic because it works in all dimensions, on any input size, and for any set of monomials used to define certain S-threshold function. Even though the formula is very generic it gives some improvements of the well-known results.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Galois field (GF) expressions are analytical representations of multiple-valued functions. For practical applications it is important to provide fast algorithms for computing coefficients in these expressions. From the FFT-theory point of view, these algorithms are Cooley-Tukey type algorithms based on the Good-Thomas factorization derived from the Kronecker product structure of the GF-transform matrices. These algorithms are good for reducing the number of operations in Central Processing Unit (CPU) implementations. When implemented over Graphics Processing Units (GPUs), the address arithmetic becomes an important factor determining the efficiency of the implementations, due to the differences between the CPU and GPU based architectures and the corresponding programming philosophies. In this paper, we define the constant geometry algorithms for computing the coefficients in GF-expressions by an analogy with the corresponding algorithms in Fourier analysis on finite Abelian groups. We performed an experimental verification of the proposed algorithms compared to the Cooley-Tukey algorithms over two GPU platforms (Nvidia and AMD) and two programming environments (CUDA and OpenCL) with the corresponding CPU implementations. The speedup achieved by constant geometry algorithms increases with the number of variables and, therefore, the constant geometry algorithms are more advantageous in the case of functions with a larger number of variables.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Solving combinatorial optimization problems via their reduction to Boolean MinSAT is an emerging generic problem solving approach. In this paper we extend MinSAT with many-valued variables, and refer to the new formalism as Many-Valued MinSAT. For Many-Valued MinSAT, we describe an exact solver, Mv-MinSatz, which builds on the Boolean branch-and-bound solver MinSatz, and exploits the domain information of many-valued variables. Moreover, we also define efficient and robust encodings from optimization problems with many-valued variables to MinSAT. The empirical results provide evidence of the good performance of the new encodings, and of Many-Valued MinSAT over Boolean MinSAT on relevant optimization problems.
    No preview · Conference Paper · May 2014
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    ABSTRACT: The live implantation of micro-electrode arrays allows the observation of populations of neural activity. There is a strong need for unsupervised adaptable neural spike extraction and spike-sorting methods, which would significantly reduce data throughput and allow for implantation and wireless transmission. We present a method for neural spike feature-extraction that involves the generation and use of a fuzzy c-means codebook. A dual-threshold spike detector isolates action potentials, and arithmetic circuits are used to extract features. Simulations show that only seven features are needed for effective template matching. Feature extraction improves neural signal compression by 87% compared to spike detection alone, possibly enabling wireless capability and hence implantation.
    No preview · Conference Paper · May 2014
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    ABSTRACT: Hintikka's game theoretic semantics for classical connectives and quantifiers has been generalized to many-valued logics in various ways. After providing a short overview, we introduce a new type of semantic games: backtracking games, where a stack of formulas is used to store information on how to continue the game even after reaching an atomic formula. We present backtracking games for the three fundamental t-norm based logics: Lukasiewicz, Gödel, and Product logic and provide corresponding adequateness theorems.
    No preview · Conference Paper · May 2014