Microelectronics Journal (MICROELECTRON J)

Publisher: Elsevier

Journal description

Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on semiconductor technology. Coverage of the journal falls into the two main categories of Circuits and Systems and Physics and Devices. The journal invites research and application papers in all the areas listed below. Papers featuring novel system designs or devices are especially welcomed. The journal also considers comprehensive review/survey papers covering recent developments. The journal's coverage includes, but is not limited to: Circuits and Systems Analogue, digital and RF circuit design methodologies Logic, architectural and system level synthesis Testing, design for testability, built in self-test Area, power and thermal evaluation Co-design, including hardware-software and chip-package Mixed-domain simulation and design Formal verification Application aspects such as signal and image processing, sensor and actuator design, reliability and quality issues, and economic models, are also welcome. Physics and Devices Materials growth science: technology and techniques Physics, properties and characterisation of materials systems Devices and microsystems technology: production and manufacturing Advanced lithography for submicron devices and VLSI microlithography Nanoelectronics and nanoprecision instrumentation Technology and applications of magnetic materials Molecular engineering: molecular materials and self-assembly processes Devices covered include semiconductor devices, optoelectronic devices, micromachined devices, nanodevices and hybrid devices. Papers covering the associated materials, physics, properties, fabrication and manufacturing of these devices are also welcomed. Journal homepages: www.elsevier.nl/locate/mejo www.elsevier.com/locate/mejo www.elsevier.co.jp/locate/mejo

Current impact factor: 0.84

Impact Factor Rankings

2016 Impact Factor Available summer 2017
2014 / 2015 Impact Factor 0.836
2013 Impact Factor 0.924
2012 Impact Factor 0.912
2011 Impact Factor 0.919
2010 Impact Factor 0.787
2009 Impact Factor 0.778
2008 Impact Factor 0.859
2007 Impact Factor 0.609
2006 Impact Factor 0.651
2005 Impact Factor 0.35
2004 Impact Factor 0.483
2003 Impact Factor 0.565
2002 Impact Factor 0.457
2001 Impact Factor 0.333
2000 Impact Factor 0.608
1999 Impact Factor 0.363
1998 Impact Factor 0.345
1997 Impact Factor 0.227

Impact factor over time

Impact factor
Year

Additional details

5-year impact 0.92
Cited half-life 6.80
Immediacy index 0.11
Eigenfactor 0.00
Article influence 0.22
Website Microelectronics Journal website
Other titles Microelectronics journal (Online)
ISSN 0026-2692
OCLC 39061766
Material type Document, Periodical, Internet resource
Document type Internet Resource, Computer File, Journal / Magazine / Newspaper

Publisher details

Elsevier

  • Pre-print
    • Author can archive a pre-print version
  • Post-print
    • Author can archive a post-print version
  • Conditions
    • Authors pre-print on any website, including arXiv and RePEC
    • Author's post-print on author's personal website immediately
    • Author's post-print on open access repository after an embargo period of between 12 months and 48 months
    • Permitted deposit due to Funding Body, Institutional and Governmental policy or mandate, may be required to comply with embargo periods of 12 months to 48 months
    • Author's post-print may be used to update arXiv and RepEC
    • Publisher's version/PDF cannot be used
    • Must link to publisher version with DOI
    • Author's post-print must be released with a Creative Commons Attribution Non-Commercial No Derivatives License
    • Publisher last reviewed on 03/06/2015
  • Classification
    green

Publications in this journal

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a low power, high data rate transceiver for passive RFID tags. Asymmetric communication link between the reader and the tag was employed to overcome the passive systems׳ power constraints while providing higher data rates. For the uplink, a low power, digital Impulse Radio Ultra-wideband (IR-UWB) transmitter was employed to send large amounts of data from the several tags to the reader while maintaining the low power requirements. The uplink can achieve data rates as high as 100 Mbps using BPSK modulation. On the other hand, the ISM band was used for the downlink. The downlink features slower data rate of 100 Kbps and utilizes a new modulation scheme that is more suitable for passive systems. The proposed transceiver was designed and simulated in 28-nm CMOS technology.
    No preview · Article · Dec 2015 · Microelectronics Journal
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    ABSTRACT: This paper presents a linearization technique to reduce harmonic distortion in a discrete-time parametric amplifier (DTPA). The technique may be applied to other variants of the DTPA, such as the complementary discrete-time parametric amplifier (CDTPA), the reverse discrete-time parametric amplifier (RDTPA), and the double-complementary discrete-time parametric amplifier (DCDTPA), to achieve similar, consistent, reductions in harmonic distortion. The parametric amplifier with and without the distortion-reducing linearization scheme was simulated for a standard 0.13 μm CMOS technology, with a sampling frequency of 250 MS/s and a 1.2 V power-supply voltage. The proposed technique shows 10 dB of mean reduction in the third-harmonic for a DTPA. Experimental results show a mean reduction in the third harmonic of 6 dB for a pMOS DTPA. The results exhibit consistent reduction in distortion for almost any input amplitude and any input common-mode voltage, without reduction in gain, without reduction in drive capability, and without any extra area requirement.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 μm CMOS process confirm the theoretically obtained results.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: This paper presents two Operational Transconductance Amplifier (OTA) compensation schemes for multistage topologies. The solutions are based on interleaved feedforward paths that cancel a non-dominant pole similarly to the zero nulling resistor technique with the advantage of avoiding resistors. Both schemes are designed in 90 nm CMOS process, the first one obtains 71 dB of DC gain, a gain bandwidth product (GBW) of 720 MHz with 360 μW of power consumption. The second proposed scheme obtains a similar DC gain and doubles the former proposed OTA GBW at the expense of 2.2 mW of power consumption for high speed applications. The compensation schemes are theoretically analyzed and the design guidelines are presented. The results of post layout simulations and corner analysis validate the new solutions.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm2 and 0.08 mm2, respectively.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: A variety of smart imaging and neuromorphic applications perform time-domain image acquisition in order to imitate biological systems and reduce the growing transmission bandwidth of the modern imaging devices. Because they operate in time-domain, they require the highest possible pixel responsivity and response speed. This work provides a comparative experimental study of different unconventional photodetecting structures with respect to these parameters. Several on-chip photodetecting device structures are designed using a low-cost standard 0.18μm CMOS process. The comparison in terms of measured quantum efficiency, light responsivity and the response speed is presented between conventional and comb-shaped N-well/P-substrate photodiodes, conventional and comb-shaped, vertical and lateral photo-bipolar-junction-transistors (photo-BJTs) and a Darlington pair of bipolar-junction phototransistors. The photodetectors are embedded in a conventional three transistor active pixel topology and measured using a customized low-cost measurement setup. The pixel quantum efficiency, responsivity and response speed are measured for each structure and the results are presented in detail. The obtained results demonstrate the benefits of using standard-CMOS-compatible BJT structures in time-domain applications. The BJT-based photodetectors show increased responsivity to green-yellow light region (500-600 nm wavelength) compared to conventional N-well/P-substrate diode. The highest responsivity is achieved by a combination of lateral and vertical BJT. The fastest response is achieved by the rarely used Darlington pair configuration of BJTs, which demonstrates the potential benefit of using this structure for time-domain imaging applications. A low-cost measurement setup and the measurement methodology are described in detail to make the experiment reproducible for any other standard CMOS process.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: In this study, we investigate the stability problems induced by undesired coupling between input feed lines and an output transformer for a linear CMOS power amplifier using a distributed active transformer (DAT) as an output balun. We extracted the losses of the input and output transformer, the undesired coupling, and the gains of the driver and the power stages to calculate the closed-loop gain. To determine the possibility of oscillation according to the location of the driver stage related to the undesired coupling and the closed-loop gain, we investigated the stability factor and stability circle. We show that the location of the driver stage of the power amplifier can be used to manage the value of the closed-loop gain. From the analyzed results, the driver stage of the linear power amplifier should be located outside the DAT to mitigate the stability issues.
    No preview · Article · Nov 2015 · Microelectronics Journal
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    ABSTRACT: A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5 × 0.77 mm2. The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between -12.1 dB and -15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: Abstract Using Hilbert-Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time-frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time-frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time-frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: Traditional digital controls mostly use digital-analog converters to convert input and output voltages into digital coding to achieve control. This paper proposes the use of two digital ramps with two different frequencies to replace a digital-analog converter. This approach can produce seven bit resolution for the DPMW signal. In addition, we use an all-digital DLL phase correction concept to further enhance the resolution of the DPWM signal by an additional three bits, resulting in 10-bit DPWM signal resolution. The proposed circuit uses 0.35 μm CMOS processes, with a core area of 0.987 mm2, a system switching frequency of 500 KHz, an input voltage range of 3.3-4.2 V, and an output voltage range of 5 V. Output voltage measurement accuracy reaches 99%, while the system reaches efficiency of 91% with output loads of up to 500 mA.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: A scalable architecture for reducing power consumption in pipelined AC-DFA (Aho-Corasick deterministic finite automaton) tries for deep packet inspection (DPI) system is proposed. A new scheme for deciding the strides of the AC-DFA trie is devised where the stride of each pipeline is decided variably to reduce the power consumption. Scaling down the clock frequency of the rarely-used stages is applied to reduce wasted power consumption. As a result, a DPI system with the proposed schemes shows a reduction of up to 27% in power consumption, compared with the state-of-the-art DPI systems.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: A novel calibration algorithm is presented for the 16-bit voltage-mode R-2R Digital-to-Analog converter (DAC). The proposed calibration can be realized with only some digital circuits and an additional calibrating DAC (CaliDAC) identical to the main DAC (MDAC) added. With the weighing-coefficient compressing technology (WCT) adopted, the nonlinearity of the CaliDAC can be compressed when the calibration is implemented, therefore leaving almost no effect on the output. Adopting the segment-calibration technology (SCT), the integral nonlinearity (INL) errors of the output can be calibrated segment by segment. With the proposed calibration algorithm, the INL errors in the final output can be calibrated successfully in the range of [-0.5LSB, 0.5LSB] for 16-bit voltage-mode R-2R DAC.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: Three-stage PLL with a Dual-Edge Phase-frequency Detector (DE-PFD) is proposed to reduce the locking time and to reduce jitter when locked. The DE-PFD speeds up the locking time by detecting the phase difference between the reference clock signal and the PLL׳s feedback signal of the divider circuit in both the rising edge and the falling edge. Meanwhile, the control signal generated from the DE-PFD can switch the loop bandwidth automatically. The locking status detection using DE-PFD saves the hardware overhead and switches the bandwidth smoothly. The DE-PFD is switched to the single-edge PFD to decrease the jitter further when the PLL is locked. The implemented proposed three-stage 1.6 GHz PLL under the TSMC 0.18 μm CMOS process shows the pre-simulation result of 56% locking time improvement as compared to the conventional PLL and the measured results of the RMS jitter reduced from 13.36 to 11 ps and the peak-to-peak jitter from 60 ps to 44 ps. When the bandwidth switching mechanism is activated, the power level of interference is reduced by 10 dBm.
    No preview · Article · Oct 2015 · Microelectronics Journal
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    ABSTRACT: In this paper, pixel circuit using mirroring structure with Indium-Gallium-Zinc oxide (IGZO) thin film transistors (TFTs) for active matrix organic light emitting diode (AMOLED) display is proposed. This pixel circuit consists of only four TFTs, and one capacitor. Due to the mirroring structure, characteristic of the driving TFT can be precisely sensed by the sensing TFT, which is deployed in a discharging path for gate electrode of the driving TFT. This discharging process is strongly dependent on threshold voltage (VT) and effective mobility of the sensing TFT. Circuit operating details are discussed, and compensation effects for threshold voltage shift and mobility variations are verified through numerical derivation and SPICE simulations. Furthermore, compared with conventional schematics, the proposed pixel circuit might have much simplified external driving circuits, and it is a promising alternative solution of high performance AMOLED display.
    No preview · Article · Oct 2015 · Microelectronics Journal