Recent publications
The effective potential approach was successfully incorporated as a quantum correction to a Monte Carlo device simulator of n-FinFETs to take into account the electron quantum confinement. The electron line density calculated by the effective potential approach agrees very well with the one calculated by a 2D Schrödinger–Poisson solver. Next, the results for the drain current as a function of the gate and drain voltage obtained by the semiclassical and by the quantum-corrected Monte Carlo device simulator were compared. The quantum-corrected Monte Carlo device simulator properly models volume inversion, which reduces the impact of surface roughness scattering, thus improving the electron drift velocity. Additionally, the quantum correction allows the modeling of the reduction of electron density in the n-FinFETs channel due to the quantum-mechanical size quantization effect. This, in turn, leads to a reduction of the drain current.
Charge hopping transport is typically modeled by Marcus theory with the coupling strengths and activation energies extracted from the constrained density functional theory. However, such a method may not be a practical route for amorphous materials due to the tremendous amount of hopping paths, therefore computationally unreachable. This work presents a general approach combining the a b initio method and model Hamiltonian, yielding similar results to constrained density functional theory. Such an approach is computationally efficient, allowing us to consider all 23 220 hopping paths between oxygen vacancies in our demonstrated amorphous hafnium dioxide model containing 324 atoms. Based on these hopping rates, charge mobility in amorphous hafnium dioxide is investigated as a function of oxygen vacancies concentration. It is found that a minimum oxygen vacancies concentration of 0.7 × 10 21 cm⁻³ is required to enable the connectivity of the charge hopping network.
The frequency of vanadium dioxide (VO2) oscillators is a fundamental figure of merit for realization of neuromorphic circuits called oscillatory neural networks (ONNs), since the high frequency of oscillators ensures low-power consuming, real-time computing ONNs. In this work, we perform electrothermal 3D Technology Computer-Aided Design (TCAD) simulations of a VO2 relaxation oscillator. We find that there exists an upper limit to its operating frequency, where such limit is not predicted from purely circuital model of VO2 oscillator. We investigate the intrinsic physical mechanisms that give rise to this upper limit. Our TCAD simulations show that there is a dependence on frequency of the points of the curve current vs voltage across VO2 device correspondent to Insulator-to-Metal Transition (IMT) and Metal-to Insulator Transition (MIT) in VO2 channel during oscillation, below some threshold values of Cext. This implies that the condition for self-oscillatory regime may be satisfied by a given load-line in low frequency range but not anymore at higher frequencies, with consequent suppression of oscillations. We notice that such variation of IMT/MIT points below some threshold values of Cext is due to a combination of different factors: intermediate resistive states achievable by VO2 channel, and interplay between frequency and heat transfer rate. The upper limit of frequency that we extract is necessarily linked to the specific VO2 device we simulate. However, our findings apply qualitatively to any VO2 oscillator. Overall, our work elucidate the link between electrical and thermal behavior in VO2 device that sets a constraint over the upper values of operating frequency of any VO2 oscillator.
The Effective Potential approach was successfully incorporated as a quantum correction to a Monte Carlo simulator of n -FinFETs to take into account the electron confinement in nanoscale n -FinFETs. The electron line density calculated by the Effective Potential approach agrees very well with the one calculated by a Schrödinger-Poisson solver. We compared the results obtained by the semiclassical and quantum-corrected Monte Carlo simulator. The quantum-corrected Monte Carlo device simulator can predict volume inversion, which reduces the impact of surface roughness scattering, improving the electron velocity. Additionally, the quantum corrections allow the modelling of the reduction of electron density in the n -FinFETs channel. This is a result of the reduced density of states in two-dimensional confined transistors and degrades the on-current in comparison with the one predicted by a semiclassical Monte Carlo simulator.
Fluorocarbon dry etching of vertical silica-based structures is essential to the fabrication of advanced complementary metal-oxide-semiconductor and dynamic random access memory devices. However, the development of etching technology is challenged by the lack of understanding of complex surface reaction mechanisms and by the intricacy of etchant flux distribution on the feature-scale. To study these effects, we present a three-dimensional, TCAD-compatible, feature-scale modeling methodology. The methodology combines a level-set topography engine, Langmuir kinetics surface reaction modeling, and a combination of reactant flux evaluation schemes. We calibrate and evaluate our model to a novel, highly selective, etching process of a SiO2 via and a Ru hardmask by CF4/C4F8. We adapt our surface reaction model to the novel stack of materials, and we are able to accurately reproduce the etch rates, topography, and critical dimensions of the reported experiments. Our methodology is therefore able to prototype and study novel etching processes and can be integrated into process-aware three-dimensional device simulation workflows.
This paper investigates the short channel effects (SCE) of the recently proposed Singular Point Source MOS (S-MOS) SiC MOSFET. The study was carried out using 2D and 3D TCAD simulations for a planar, trench and S-MOS 1200V SiC MOSFETs for the IV output characteristics up to 1200V and under short circuit transient conditions. The S-MOS device shows no SCE up to the rated voltage when compared to reference planar and trench devices which exhibit strong SCE. This is due to the appropriate P++ protection of the N++ source and the electric field shielding due to the narrow mesa dimensions between orthogonal trenches where the channel is located.
Because of their nonvolatile nature and simple structure, the interest in MRAM devices has been steadily growing in recent years. Reliable simulation tools, capable of handling complex geometries composed of multiple materials, provide valuable help in improving the design of MRAM cells. In this work, we describe a solver based on the finite element implementation of the Landau–Lifshitz–Gilbert equation coupled to the spin and charge drift-diffusion formalism. The torque acting in all layers from different contributions is computed from a unified expression. In consequence of the versatility of the finite element implementation, the solver is applied to switching simulations of recently proposed structures based on spin-transfer torque, with a double reference layer or an elongated and composite free layer, and of a structure combining spin-transfer and spin-orbit torques.
The level-set method is widely used in expanding front simulations in numerous fields of computational research, such as computer graphics, physics, or microelectronics. In the latter, the level-set method is employed for topography simulations of semiconductor device fabrication processes, being driven by complicated physical and chemical models. These models tend to produce surfaces with critical points where accuracy is paramount. To efficiently increase the accuracy in regions neighboring these critical points, automatic hierarchical domain refinement is required, guided by robust feature detection. Feature detection has to be computationally efficient and sufficiently accurate to reliably detect the critical points. To that end, we present a fast parallel geometric feature detection algorithm for three-dimensional level-set functions. Our approach is based on two different, complementary curvature calculation methods of the zero level-set and an optimized feature detection parameter to detect features. For performance reasons, our algorithm can be in principal linked to different curvature calculation methods, however, as will be discussed, two particularly attractive options are available: (i) A novel extension of the standard curvature calculation method for level-set functions, and (ii) an often disregarded method for calculating the curvature due to its purported low numerical accuracy. We show, however, that the latter is still a viable option, and that our algorithm is able to reliably detect features on geometries stemming from complicated, practically relevant geometries. Our algorithm and findings are applicable to other fields of applications such as surface simplification.
Designing advanced single-digit shape-anisotropy MRAM cells requires an accurate evaluation of spin currents and torques in magnetic tunnel junctions (MTJs) with elongated free and reference layers. For this purpose, we extended the analysis approach successfully used in nanoscale metallic spin valves to MTJs by introducing proper boundary conditions for the spin currents at the tunnel barrier interfaces, and by employing a conductivity locally dependent on the angle between the magnetization vectors for the charge current. The experimentally measured voltage and angle dependencies of the torques acting on the free layer are thereby accurately reproduced. The switching behavior of ultra-scaled MRAM cells is in agreement with recent experiments on shape-anisotropy MTJs. Using our extended approach is absolutely essential to accurately capture the interplay of the Slonczewski and Zhang-Li torque contributions acting on a textured magnetization in composite free layers with the inclusion of several MgO barriers.
Volatile memristors are versatile devices whose operating mechanism is based on an abrupt and volatile change of resistivity. This switching between high and low resistance states is at the base of cutting edge technological implementations such as neural/synaptic devices or random number generators. A detailed understanding of this operating mechanisms is essential prerequisite to exploit the full potentiality of volatile memristors. In this respect, multi-physics device simulations provide a powerful tool to single out material properties and device features that are the keys to achieve desired behaviors. In this paper, we perform 3D electrothermal simulations of volatile memristors based on vanadium dioxide (VO2) to accurately investigate the interplay among Joule effect, heat dissipation and the external temperature T0 over their resistive switching mechanism. In particular, we extract from our simulations a simplified model for the effect of T0 over the negative differential resistance (NDR) region of such devices. The NDR of VO2 devices is pivotal for building VO2 oscillators, which have been recently shown to be essential elements of oscillatory neural networks (ONNs). ONNs are innovative neuromorphic circuits that harness oscillators’ phases to compute. Our simulations quantify the impact of T0 over figures of merit of VO2 oscillator, such as frequency, voltage amplitude and average power per cycle. Our findings shed light over the interlinked thermal and electrical behavior of VO2 volatile memristors and oscillators, and provide a roadmap for the development of ONN technology.
This paper presents a Singular Point Source MOS (S-MOS) cell concept suitable for SiC MOSFETs targeting low conduction losses, low switching losses and high robustness. The S-MOS concept differs from standard Planar or Trench MOS cells in the manner by which the total channel width per device area is determined. For the proof of concept and device electrical performance evaluation, the paper will provide 2D and 3D TCAD simulations results for 1200V SiC MOSFETs including the S-MOS and reference planar and trench structures.
Smart textiles consist of discrete devices fabricated from—or incorporated onto—fibres. Despite the tremendous progress in smart textiles for lighting/display applications, a large scale approach for a smart display system with integrated multifunctional devices in traditional textile platforms has yet to be demonstrated. Here we report the realisation of a fully operational 46-inch smart textile lighting/display system consisting of RGB fibrous LEDs coupled with multifunctional fibre devices that are capable of wireless power transmission, touch sensing, photodetection, environmental/biosignal monitoring, and energy storage. The smart textile display system exhibits full freedom of form factors, including flexibility, bendability, and rollability as a vivid RGB lighting/grey-level-controlled full colour display apparatus with embedded fibre devices that are configured to provide external stimuli detection. Our systematic design and integration strategies are transformational and provide the foundation for realising highly functional smart lighting/display textiles over large area for revolutionary applications on smart homes and internet of things (IoT).
Thin-film transistors based on amorphous oxide semiconductors could be used to create low-cost backplane technology for large flat-panel displays. However, a trade-off between mobility and stability has limited the ability of such devices to replace current polycrystalline silicon technologies. Here we show that the sensitivity of amorphous oxide semiconductors to externally introduced impurities and defects is determined by the location of the conduction-band minimum and the relevant doping ability. Using bilayer-structured thin-film transistors, we identify the exact charge-trapping position under bias stress, which shows that the Fermi-level shift in the active layer can occur via electron donation from carbon-monoxide-related impurities. This mechanism is highly dependent on the location of the conduction-band minimum and explains why carbon-monoxide-related impurities greatly affect the stability of high-mobility indium tin zinc oxide transistors but not that of low-mobility indium gallium zinc oxide transistors. Based on these insights, we develop indium tin zinc oxide transistors with mobilities of 70 cm2 (V s)–1 and low threshold voltage shifts of –0.02 V and 0.12 V under negative- and positive-bias temperature stress, respectively.
In this article we present a full physical analytical model (FAM) for symmetric double-gate amorphous oxide semiconductor TFTs (DG AOSTFTs). The current–voltage (I–V) model is physically described for the above-threshold operation regime. In this case, the general expression for the field effect mobility is evaluated for the potential at the centre of the semiconductor layer at V G= 1 + V T, obtaining the value of the mobility parameter called µ 1DG for DG-AOSTFT. This parameter can now be used to represent the field effect mobility expression like in the model known as the unified model and extraction method, which is widely used for modelling amorphous devices. The proposed FAM model contains the analytical capacitances–voltage (C–V) model and considers the specific characteristics of DG structures, including the potential different from zero, at the centre of the semiconductor layer. The model was described in Verilog-A for introducing in Silvaco’s SmartSpice simulation program and was validated with simulated data and experimental characteristics of reported DG amorphous indium-galium-zinc oxide devices.
We study the effect of Gaussian energetic disorder on the organic field-effect transistors (OFETs) with surprisingly high field-effect mobility and the low contact resistance. The numerical device simulation assumes the thermally assisted hopping transport and injection in disordered semiconductors. The results are analyzed with the power-law field-effect mobility and the asymptotic power-law contact resistance model. Transistor parameters extracted by the models reveal that a higher Gaussian disorder, which leads to a lower injection barrier and a larger mobility enhancement, is the origin of the high field-effect mobility and the low contact resistance.
Benchmarks are essential to support the evolution of EDA environments. Usually, different methods are compared through reference circuits, allowing their relative performance analysis. However, such an assessment does not indicate how the obtained solutions are far from the optimal circuit building. A novel benchmark suite with known exact solution is presented for the logic synthesis design process. Those benchmark circuits have been synthesized on FPGA and ASIC design flows, showing that there is a room for further improvement on IC design tools.
A common problem arising in expanding front simulations is to restore the signed distance field property of a discretized domain (i.e., a mesh), by calculating the minimum distance of mesh points to an interface. This problem is referred to as re-distancing and a widely used method for its solution is the fast marching method (FMM). In many cases, a particular high accuracy in specific regions around the interface is required. There, meshes with a finer resolution are defined in the regions of interest, enabling the problem to be solved locally with a higher accuracy. Additionally, this gives rise to coarse-grained parallelization, as such meshes can be re-distanced in parallel. An efficient parallelization approach, however, has to deal with interface-sharing meshes, load-balancing issues, and must offer reasonable parallel efficiency for narrow band and full band re-distancing. We present a parallel multi-mesh FMM to tackle these challenges: Interface-sharing meshes are resolved using a synchronized data exchanges strategy. Parallelization is introduced by applying a pool of tasks concept, implemented using OpenMP tasks. Meshes are processed by OpenMP tasks as soon as threads become available, efficiently balancing out the computational load of unequally sized meshes over the entire computation. Our investigations cover parallel performance of full and narrow band re-distancing. The resulting algorithm shows a good parallel efficiency, if the problem consists of significantly more meshes than the available processor cores.
Step-controlled growth of 4H-SiC epitaxial layers leads to the formation of a step-bunched morphology along the surface with larger macrosteps, composed of smaller microsteps of several Si-C bilayer heights. As thermal oxidation is an orientation-dependent process, a multi-faceted surface is expected to exhibit a different oxidation behavior compared to a perfectly planar surface. In this work, step-bunched surfaces after oxidation are investigated by high-resolution atomic force microscopy (HR-AFM) and transmission electron microscopy (TEM) indicating a morphological change in the early stages of thermal oxidation. An orientation-dependent oxidation model is used to correctly describe variations of the oxide thicknesses at isolated macrosteps.
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