• Genève, France
Recent publications
The successful handling of large semiconductor wafers is crucial for their production on a large scale. Recently, the development of pilot lines using 8" wide band gap substrates, such as silicon carbide, has brought about similar challenges. Early-stage warpage control is essential to prevent uncontrolled asymmetric warpage, known as wafer bifurcation or buckling, which can occur with 8" 4H-SiC substrates, too. Moreover, the manufacturing process for large 4H-SiC wafers can be challenging due to warping during finishing and processing. Even in a gravity-free environment, thinning an 8" or 12" wafer can result in warpage and bifurcation. To mitigate this issue, the taiko method, which involves creating a thicker ring region around the rim of the wafer, has been widely used. Previous research has focused on the theoretical factors affecting the warpage of a backside metalized taiko wafer. This study extends the case of a front-side metalized taiko wafer and introduces the concept of the equivalent thickness to a 4H-SiC large taiko wafer. The equivalent thickness lies between the thickness of the central region and the annular region due to the influence of the ring region. Modelling can be helpful due to the limited number of taiko wafers that can be produced in a production line. In the investigation we developed both an analytical approach and a finite element analysis (FEA) with ANSYSY® software to model the equivalent thickness of a 4H-SiC taiko wafer. We investigated the curvature as a function of the stress of the metal layer, considering key design factors such as the substrate region thickness, thin metal film thickness, step height, and width of the annular ring region. By systematically varying the thickness of the central region of the taiko wafer, we investigated the curvature as a function of stress induced by thermal loads in the linear regime. The aim of this study is to identify regularities and similarities with the Stoney equation and investigate the validity of the analytical approach for the case of a 4H-SiC substrate.
Image processing algorithms on FPGAs have increasingly become more pervasive in real-time vision applications. Such algorithms are computationally complex and memory intensive, which can be severely limited by available hardware resources. Optimisations are therefore necessary to achieve better performance and efficiency. We hypothesise that, unlike generic computing optimisations, domain-specific image processing optimisations can improve performance significantly. In this paper, we propose three domain-specific optimisation strategies that can be applied to many image processing algorithms. The optimisations are tested on popular image-processing algorithms and convolution neural networks on CPU/GPU/FPGA and the impact on performance, accuracy and power are measured. Experimental results show major improvements over the baseline non-optimised versions for both convolution neural networks (MobileNetV2 & ResNet50), Scale-Invariant Feature Transform (SIFT) and filter algorithms. Additionally, the optimised FPGA version of SIFT significantly outperformed an optimised GPU implementation when energy consumption statistics are taken into account.
This paper proposes an innovative concept of spatial third-order intermodulation products (IMD3) filtering in millimeter-wave 5G phased arrays. This technique aims to relax the linearity constraints on the power amplifiers (PA) and thus power consumption. Implementation of independent control of the phase of IMD3 is proposed by using the nonlinear output capacitance of metal-oxide semi-conductors (MOS) amplifiers under phase-controlled second harmonic injection. The implemented control uses beamforming properties to perform spatial filtering of IMD3 product. A second harmonic injection on a power amplifier is proposed in STMicroelectronics CMOS065SOIMMW technology at 28 GHz. It shows phase control of IMD3 with a range of 35 degrees, allowing relaxation up to 17 dB on the linearity of large phased array power amplifiers.
Fluorinated chemistries can lead to severe corrosion damage towards silicon and germanium based materials when wafers have a significant amount of electrostatic charges. This corrosion is evidenced on both single wafer and batch tools. It can be prevented by the presence of enough light, and wafer charging can also be eradicated by photo emission with UV light.
Photoresist after implantation is commonly removed either by wet chemical dissolution with sulfuric acid, or by dry ash stripping followed with a wet cleaning. To prevent any photoresist residues, sulfuric acid is still conserved in post ash cleans as additional safety. However, by ensuring sufficient over ash time, SPM (Sulfuric acid Peroxide hydrogen Mixture) chemical need becomes less essential. This paper reevaluates the benefit of SPM after dry ash stripping regarding the environmental context. The advantages of dry ash stripping with clean, compared to wet stripping are outlined. The study introduces prior analyses on defectivity and material consumption. Finally, device matching and yield stability, defined as the main success criteria, are described.
This paper offers a preliminary study for the analysis of metallic contamination on front-end patterned wafers obtained by two different techniques based on the etching of the whole patterns, LPD-Bulk and VPD-Bulk coupled with an ICPMS. To elaborate the analysis of patterned wafers, methods were first verified and optimised on reference Si wafers. Both techniques are complementary methods for the etching of wafers. LPD-Bulk enables a fast etching of several micrometres of Si but with less precision than VPD-Bulk, which is more adapted for the etching of layers thinner than 1 micrometre. The intentional contamination in SC1 and H 2 O bath of monitoring wafers showed that contamination in H 2 O is better controlled due to the absence of chemical reactions, competition between oxidation and etching processes occurring during SC1. And diffusion of contaminants at the tested temperatures from 20°C to 80°C, does not occur. Heat treatment should be applied to allow the diffusion of metallic contaminants in the bulk of the wafers.
In this paper, we investigate the use of a wet cleaner developed to dissolve residues left after plasma etching selectively to aluminum in new applications such as the removal of various resilient ionic and halides-based surface contaminants. The compromise between efficiency and selectivity of this fluorinated acid cleaner makes it an interesting chemistry for many cleaning steps during wafer manufacturing. Two new applications were investigated: the selective removal of fluoride-based defects on aluminum pads and surface decontamination of various ionic metals with low substrate consumption. These studies showed very encouraging results in beakers level tests, but also on partly industrial equipment, opening new possibilities for this cleaner. Indeed, “water lily” defects removal seems to be possible with a low aluminum consumption in TechniClean IK73. Decontamination study carried out in static bath and in single wafer tool showed rather similar results, enabling static bath protocol and ionic metals removal to be validated and VPD-ICPMS results, after a short process time in a single wafer tool were very promising with metal levels close to the lower limit of detection of all elements tested.
Pattern collapse in CMOS image sensors is discussed, where silicon pillars are separated by trenches of few microns deep. Both analytical and numerical models are given and match experimental results. The trench profile is also taken into account to predict such collapse.
The removal of particle contamination is key to maximize yield. Some common particle removal techniques are not relevant anymore when complex and fragile structures are present on the surface. This led to the development of new cleaning processes based on innovative concepts to improve particle removal efficiency without any pattern damage. Some of these processes rely on a resist film lift off. One of these particle removal processes is studied in this paper. The process consists in some resist spin-coating followed by a diluted ammonia dispense to remove this film, which results in particle removal. This specific resist film is made of two immiscible organic polymers. A study was conducted to understand how the organization of these two polymers in the film is key for the film lift-off and the cleaning efficiency. This organization was shown to depend on the substrate contact angle and the resist formulation. A surface preparation is required on hydrophobic surface to reduce their water contact angle and ensure the efficiency of the process. As a result, compared to a high velocity aerosol cleaning technique, this resist peeling process requires multiple steps and a significant process time. A Particle Removal Efficiency study was then performed on blanket wafers to determine and understand how the different process parameters impacted on the cleaning efficiency. It led to the optimization of this process efficiency on blanket wafers. A comparison between an optimized process and a high velocity aerosol cleaning technique underlined the potential of such a process. Compared to high velocity aerosol cleaning, it demonstrated higher efficiency on blanket wafers, without causing any pattern damage on patterned wafers. These results lead to promising perspectives for using this process in the cleaning of fragile structure or targeting small particles with high adhesion.
Defects induced by 62 MeV protons in SPADs are studied. A study of the Dark Count Rate (DCR) variation after irradiations for different biasing conditions underlines the predominance of field enhancement effects such as Poole-Frenkel effect and phonon-assisted-tunneling over band-to-band tunneling. Activation energy measurements below mid-gap value confirm the important contribution of these field effects. However, unexpected behaviors in these energies are seen: very low activation energies are extracted for SPADs with a DCR induced around 10 <sup xmlns:mml="" xmlns:xlink="">3</sup> counts per second. We attribute them to the contribution of different groups of defects, with different energy level distribution. This analysis is completed with an annealing study between 100 °C and 300 °C. Results for high DCR SPADs correlate well with the presence of defect clusters. Moreover, histogram of the annealing temperature at which the DCR starts to drop displays two peaks at 170 °C and 250 °C. The first one is attributed to phosphorus vacancies and complex cluster of defects with an energy distribution inside the Si bandgap centered above mid-gap. The second one is attributed to clusters of divacancies that also anneal at temperatures around 250 °C.
Dark current degradation, origins, and annealing behavior after x-ray irradiation are studied in a P-type, hole collecting, backside-illuminated image sensor currently being developed at STMicroelectronics and based on deep-trenched photo-MOS pixels. Different biasing conditions during irradiation, i.e. grounded or biased and sequenced, are compared. The dark current increase with total ionizing dose (TID) and the dark current annealing behavior seem to be driven by the backside interface between the P-epitaxy of the pixels and the ONO stack. Despite still being under development, this pixel architecture already exhibits both very good electro-optical performance and a better radiation hardness than pinned photodiode-based CMOS Image sensors that benefit from the same advanced CIS processing technologies. At high total dose range, the photogate challenges custom Radiation-Hardened-by-Design photodiodes by exhibiting a comparable radiation tolerance while bringing new features such as high-resolution or Correlated Double Sampling.
This work presents a new type of Charge Coupled Device (CCD) manufactured using a CMOS process and featuring Capacitive Deep Trench Isolation (CDTI). The device is used in a Multi-Pinned Phase mode (MPP) enabling almost constant oxide interface passivation. Flatband shift, Dark current and Charge Transfer Inefficiency (CTI) induced by Total Ionizing Dose (TID) are investigated. Despite the increase of interface states, results show that dark current can be efficiently mitigated by use of short charge transfer duration, avoiding full interface depletion and free charge generation. It is further shown that trapping by interface states is only lightly affecting CTI as the Buried Channel keeps electrons far from interfaces. Finally, a clear correlation on flatband shift with Full Well Charge (FWC) reduction is established.
The 2022 ASMC, our 33rd, returned to Saratoga Springs, NY as an in-person conference after 2 years as a virtual conference. While we are all grateful for the digital world’s enhancements that allowed this conference to be held remotely, attendees were happy to return to an in-person event where networking is much easier.
Our study details the development and validation of an orchestrator-controlled robotic network that effectively organizes and manages the activities of multiple robots. The design workflow is based on a model-driven methodology that allows for the independent specification of robot behaviour, which can be successfully refined regardless of the physical architecture. The main focus of this study involves the verification and analysis of robot orchestration by building formal models in a component–port–connector fashion supported by BIP language (behaviour–interaction–priority). The model also helps to study the automated orchestration with the help of a centralized computer tasks manager. The related functional requirements gathered from industrial partners are specified in temporal logic. Statistical model checking is performed to verify the model’s correctness, providing a functional assurance to achieve the deployment. Validation is a carry out using a dedicated robotic platform simulator. We demonstrate the capability of the verification artefact for the Brain-IoT ( platform and ways of applying them to potentially complex case studies.
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Giuseppe Ferla
  • Research & Development
Luca Celetto
  • Advanced System Technology
Mirko Guarnera
  • ST Central Labs
Claudio Adragna
  • AMS - I&PC Division
Pascal Chevalier
  • Digital, Non-Volatile Memories, Analog Devices and Integration
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