Intel
  • Santa Clara, United States
Recent publications
Virtualization on a client system (like a laptop) to support additional Operating Systems (OS) is becoming critical and is a rapidly evolving market space. Vendors like Microsoft, Google are providing inbuilt virtual machines (VM) that allows Linux environment (as Guest OS) on a Windows machine or Chromebook without need of dual booting. This multi-OS support is aimed to boost productivity and to transform user experience in a single platform by providing access to Guest OS’s apps to work, develop, study, test, and play. When engineering such virtual OS environments, it is important to advance every aspect of developer experience including development tool in the new single platform solution with same native experience. One of the main obstacles for such computing experience is the lack of hardware availability in a single platform. For an example, Android OS, a device OS, acts as a USB device when connected to a host for development & debugging. But when Android OS runs as a Guest OS on Chromebook, it lacks USB device mode support for development & debugging. This paper explains how Android OS running as a guest OS on a Chromebook can extend its support to Android Debug Bridge (ADB), a development and debug tool with USB device mode. In the process the paper explains how USB 3.x extensible Host Controller Interface (xHCI) offers an extended capability and how multi-OSes can be extended to guest (Android) OS to bring a native development and debug experience for ADB.
The high-angular-resolution imaging capability of future automotive and security sensing systems is in favor of compact, fully integrated, and reconfigurable antenna arrays. The adoption of sub-terahertz (sub-THz) frequencies for such systems relieves the hardware requirements for the physical size and fractional bandwidth (BW). Phased/MIMO arrays, when a large 2-D aperture size is required, are facing great challenges related to high circuit complexities, electronic density, and computation power. This article presents a digitally controlled 265-GHz reflectarray that decouples the designs of active circuits and large passive antenna array. The array is constructed using stitched CMOS chips, fabricated on Intel 16 process, and each unit adopts 1-bit phase quantization and cross-polarization backscatter approaches. With a credit-card size ( 5.6\ttimes5.6 cm 2^2 ), the reflectarray performs 1 ^\circ -wide pencil beamforming ( \sim 42-dBi directivity) and electric steering within ±\pm 60 ^\circ range in both azimuth and elevation directions. The reflectarray is also equipped with 780-Mb integrated under-antenna memory, which not only eliminates high-speed data communication during raster scan but also enables techniques such as time-dithering sidelobe reduction, and beam squint corrections. Pairing with a commercial sub-THz transceiver (TRX), this work also, for the first time, demonstrates high-angular-resolution, mechanical-movement-free terahertz (THz) imaging.
Multi-core shared memory architectures have become ubiquitous in computing hardware nowadays. As a result, there is a growing need to fully utilize these architectures by introducing appropriate parallelization schemes, such as OpenMP worksharing-loop constructs, to applications. However, most developers find introducing OpenMP directives to their code hard due to pervasive pitfalls in managing parallel shared memory. To assist developers in this process, many compilers, as well as source-to-source (S2S) translation tools, have been developed over the years, tasked with inserting OpenMP directives into code automatically. In addition to having limited robustness to their input format, these compilers still do not achieve satisfactory coverage and precision in locating parallelizable code and generating appropriate directives. Recently, many data-driven AI-based code completion (CC) tools, such as GitHub CoPilot, have been developed to ease and improve programming productivity. Leveraging the insights from existing AI-based programming-assistance tools, this work presents a novel AI model that can serve as a parallel-programming assistant. Specifically, our model, named PragFormer, is tasked with identifying for loops that can benefit from conversion to parallel worksharing-loop construct (OpenMP directive) and even predict the need for specific data-sharing attributes clauses on the fly. We created a unique database, named Open-OMP, specifically for this goal. Open-OMP contains over 32,000 unique code snippets from different domains, half of which contain OpenMP directives, while the other half do not. We experimented with different model design parameters for these tasks and showed that our best-performing model outperforms a statistically-trained baseline as well as a state-of-the-art S2S compiler. In fact, it even outperforms the popular generative AI model of ChatGPT. In the spirit of advancing research on this topic, we have already released source code for PragFormer as well as Open-OMP dataset to public. Moreover, an interactive demo of our tool, as well as a Hugging Face webpage to experiment with our tool, are already available.
As metallic nanostructures shrink towards the size of the electronic mean free path, thermal conductivity decreases due to increased electronic scattering rates. Matthiessen’s rule is commonly applied to assess changes in electron scattering rates, although this rule has not been validated experimentally at typical operating temperatures for most of the electronic systems (e.g., near room temperature). In this study, we experimentally evaluate the validity of Matthiessen’s rule in determining the thermal conductivity of thin metal films by measuring the in-plane thermal conductivity and electronic scattering rates of copper (Cu) films with varying thicknesses (27 nm — 5 µm), microstructures, and grain boundary segregation. Comparing total electron scattering rates measured with infrared ellipsometry to infrared ultrafast pump-probe measurements, we find that the electron-phonon coupling factor is independent of film thickness, whereas the total electronic scattering rate increases with decreasing film thickness. Our findings provide experimental validation of Matthiessen’s rule for electron transport in thin metal films at room temperature and also introduce an approach to discern critical heat transfer processes in thin metal interconnects, which holds significance for the advancement of future CMOS technology.
OpenMC is an open source Monte Carlo neutral particle transport application that has recently been ported to GPU using the OpenMP target offloading model. We examine the performance of OpenMC at scale on the Frontier, Polaris, and Aurora supercomputers, demonstrating that performance portability has been achieved by OpenMC across all three major GPU vendors (AMD, NVIDIA, and Intel). OpenMC’s GPU performance is compared to both the traditional CPU-based version of OpenMC as well as several other state-of-the-art CPU-based Monte Carlo particle transport applications. We also provide historical context by analyzing OpenMC’s performance on several legacy GPU and CPU architectures. This work includes some of the first published results for a scientific simulation application at scale on a supercomputer featuring Intel’s Max series “Ponte Vecchio” GPUs. It is also one of the first demonstrations of a large scientific production application using the OpenMP target offloading model to achieve high performance on all three major GPU platforms.
Flexible electronics are integral in numerous domains such as wearables, healthcare, physiological monitoring, human–machine interface, and environmental sensing, owing to their inherent flexibility, stretchability, lightweight construction, and low profile. These systems seamlessly conform to curvilinear surfaces, including skin, organs, plants, robots, and marine species, facilitating optimal contact. This capability enables flexible electronic systems to enhance or even supplant the utilization of cumbersome instrumentation across a broad range of monitoring and actuation tasks. Consequently, significant progress has been realized in the development of flexible electronic systems. This study begins by examining the key components of standalone flexible electronic systems–sensors, front‐end circuitry, data management, power management and actuators. The next section explores different integration strategies for flexible electronic systems as well as their recent advancements. Flexible hybrid electronics, which is currently the most widely used strategy, is first reviewed to assess their characteristics and applications. Subsequently, transformational electronics, which achieves compact and high‐density system integration by leveraging heterogeneous integration of bare‐die components, is highlighted as the next era of flexible electronic systems. Finally, the study concludes by suggesting future research directions and outlining critical considerations and challenges for developing and miniaturizing fully integrated standalone flexible electronic systems.
The identification of malaria infection using microscope images of blood smears is considered as a ‘gold standard’. The diagnosis of malaria needs expert microscopists which are scarce in remote areas where malaria is endemic. Therefore, it is desirable to automate the repetitive task of pathogen detection in the blood samples received as microscope images. This study provides an easy to use and deploy method for implementing a malaria pathogen detection software- the Intelligent Suite. The Intelligent Suite features a graphical user interface (GUI) implemented using ‘cvui’ library to interact with the OpenVINO’s inference engine for model optimisation and deployment across several inference devices. The intelligent Suite uses a custom YOLO-mp-3l model trained on Darknet framework for detection of malaria pathogen in thick smear microscope images. Moreover, the Intelligent Suite provides user interface for inference device/mode selection, alter model parameters, and generate detection reports along with the model performance metrics. The Intelligent Suite was executed on a CPU computer with model inference running on a plug-and-play Neural Compute Stick (NCS2) and performance reported.
Side-channel attacks (SCAs) have been shown to be very effective in breaking cryptographic engines. In this article, we present a new power obfuscation switched-capacitor (POSC) dc–dc converter. To a first-order approximation, it equalizes the charge such that the same amount of charge is drawn from the input power supply in each cycle. We evaluated the design by analyzing the power supply to an advanced encryption standard (AES) unit powered by the proposed converter. CPA fails after evaluation with 10k10k traces. Two different topologies of the switched-capacitor circuit are analyzed for their contribution to side-channel power information leakage. The three-phase POSC is designed with both switched-capacitor converters (SCC1 and SCC2) and achieves efficiency of 77% and 70%.
This paper presents a chopper instrumentation amplifier (IA) architecture with two symmetric differential negative capacitance generation feedback (NCGFB) loops. The NCGFB design technique enables to cancel parasitic capacitances of cables and electrodes at the IA input in order to boost the input impedance. The negative capacitance is generated through feedback loops containing digitally programmable capacitor banks that can compensate for an extra input capacitance of up to 100 pF. A chopping technique is also introduced to enhance the noise performance of NCGFB IAs with input impedance boosting. The proposed amplifier is based on the capacitively-coupled IA (CCIA) architecture with additional circuit-level innovations to increase input impedance and improve noise performance. Two NCGFB loops have been added to further boost the input impedance. These NCGFB loops include a low-pass filter (LPF) to suppress ripples from the chopping prior to feeding the signal back to nodes at which capacitances are cancelled. We present an analysis to verify the stability of the loops as well as their effects on boosting the input impedance. The full symmetry of the NCGFB loops enables the use of identical capacitor banks to maintain a high common-mode rejection ratio (CMRR). The IA was designed and fabricated in 65-nm CMOS technology with a 1.2V supply and consumes 2.46 μ\mu W. Chip measurements show that the IA has a 44-dB gain, 40-Hz bandwidth, a total harmonic distortion (THD) of - 44.3 dB with 35 mV pp_{\mathrm{pp}} sinusoidal output at 10 Hz, CMRR >> 90.9 dB, a 92.3 dB power supply rejection ratio (PSRR), 0.54- μ\mu V integrated input-referred noise over a bandwidth of 0.5 -40 Hz with a noise efficiency factor of 4.75, and an input impedance of 1.9 G Ω\Omega at 10 Hz even with an extra input capacitance of 100 pF.
Carriers are currently introducing 5G wireless systems at sub-6, 28, 38, 57–71, and 71–86 GHz. As 5G is commercially deployed, research into the next-generation communication systems (6G), expected to be 100–340 GHz, is beginning. Power-efficient systems operating at such high frequencies require RF front ends with transistor RF figures of merit (FOMs) such as transit frequency fτ{f}_{\tau} and maximum oscillation frequency fmax{f}_{\max} in excess of 500 GHz. Indium-phosphide (InP) heterojunction bipolar transistors (HBTs) and high-electron mobility transistors (HEMTs) are promising technologies for these extreme frequency applications.
Scalable quantum processors require high-fidelity universal quantum logic operations in a manufacturable physical platform. Donors in silicon provide atomic size, excellent quantum coherence and compatibility with standard semiconductor processing, but no entanglement between donor-bound electron spins has been demonstrated to date. Here we present the experimental demonstration and tomography of universal one- and two-qubit gates in a system of two weakly exchange-coupled electrons, bound to single phosphorus donors introduced in silicon by ion implantation. We observe that the exchange interaction has no effect on the qubit coherence. We quantify the fidelity of the quantum operations using gate set tomography (GST), and we use the universal gate set to create entangled Bell states of the electrons spins, with fidelity 91.3 ± 3.0%, and concurrence 0.87 ± 0.05. These results form the necessary basis for scaling up donor-based quantum computers.
Retinopathy is a group of retinal disabilities that causes severe visual impairments or complete blindness. Due to the capability of optical coherence tomography to reveal early retinal abnormalities, many researchers have utilized it to develop autonomous retinal screening systems. However, to the best of our knowledge, most of these systems rely only on mathematical features, which might not be helpful to clinicians since they do not encompass the clinical manifestations of screening the underlying diseases. Such clinical manifestations are critically important to be considered within the autonomous screening systems to match the grading of ophthalmologists within the clinical settings. To overcome these limitations, we present a novel framework that exploits the fusion of vision language correlation between the retinal imagery and the set of clinical prompts to recognize the different types of retinal disabilities. The proposed framework is rigorously tested on six public datasets, where, across each dataset, the proposed framework outperformed state-of-the-art methods in various metrics. Moreover, the clinical significance of the proposed framework is also tested under strict blind testing experiments, where the proposed system achieved a statistically significant correlation coefficient of 0.9185 and 0.9529 with the two expert clinicians. These blind test experiments highlight the potential of the proposed framework to be deployed in the real world for accurate screening of retinal diseases
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5,019 members
Mateusz Piotr Nowak
  • Parallel Runtimes Engineering group
Aleksandar Aleksov
  • Department of Components Research
Alexander Nadel
  • Intel, Haifa
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