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Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μ...
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Introducing the notion of transformational silicon electronics has paved the way for integrating various applications with silicon-based, modern, high-performance electronic circuits that are mechanically flexible and optically semitransparent. While maintaining large-scale production and prototyping rapidity, this flexible and translucent scheme d...
In this work, we show the performance improvement of p-type thin-film transistors (TFTs) with Ge 2 Sb 2 Te 5 (GST) semiconductor layers on flexible polyimide substrates, achieved by downscaling of the GST thickness. Prior works on GST TFTs have typically shown poor current modulation capabilities with ON/OFF ratios ≤20 and non-saturating output cha...
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... While IoT has been one of the central elements in diverse research fields such as smart cities [1]- [3], industrial applications (IIoT) [4]- [6], health care [7]- [10], transistor technologies [11]- [13], and flexible electronics [14]- [20] over the last decade, recent years have also witnessed its meteoric rise in consumer applications such as home automation, transportation, energy management, etc. However, many of these devices still use existing protocols such as Wi-Fi [21], Cellular [22], and Bluetooth [23]. ...
LoRaWAN has garnered tremendous attention owing to the low power consumption of end nodes, long range, high resistance to multipath, low cost, and use of license-free sub-GHz bands. Consequently, LoRaWAN is gradually replacing Wi-Fi and Bluetooth in sundry IoT applications including utility metering, smart cities, and localization. Localization, in particular, has already witnessed a surge of alternatives to Global Navigation Satellite System (GNSS), based on Wi-Fi, Bluetooth, Ultra Wide Band, 5G, etc. in indoor and low power domains due to the poor indoor coverage and high power consumption of GNSS. With the need for localization only shooting up with dense IoT deployments, LoRaWAN is seen as a promising solution in this context. Indeed, many attempts employing various techniques such as Time of Arrival (ToA), Time Difference of Arrival (TDoA), and Received Signal Strength Index (RSSI) have been made to achieve localization using LoRaWAN. However, a significant drawback in this scenario is the lack of extensive data on path loss and signal propagation modeling, particularly in Indian cityscapes. Another demerit is the use of GNSS at some stage primarily for time synchronization of gateways. In this work, we attempt to nullify these two disadvantages of LoRaWAN based localization. The first part of this work presents experimental data of LoRaWAN transmissions inside a typical city building to study signal propagation and path loss. The latter part proposes a standalone GNSS-free localization approach using LoRaWAN that is achieved by applying a collaborative, TDoA-based methodology. An additional stationary node is introduced into the network to allow the synchronization of gateways without GNSS. Finally, the distribution of localization error in a triangle of gateways and the effect of timing resolution, time-on-air, and duty cycle constraints on it are investigated.
... Therefore, fracture stress of chips can not be enhanced without improvising the thinning and Since silicon is piezoresistive, the electrical performance of silicon ICs change when they are stressed due to both in-built stresses resulting from IC processing [135] and externally applied stress [136,137]. Sometimes better electrical performance can be derived from the ICs when they are stressed [138,139]. Yet, it is complicated to include the bending effects of ICs in most state-of-the-art simulation tools to predict the electrical performance. Therefore, it is simpler and advantageous to have the same electrical performance for the ICs in both flat and bent state. ...
Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems.
... They also studied the mechanics of the stretchability. [10,11,23,[33][34][35][100][101][102] We believe that applying unconventional techniques to the materials for harsh environments and capitalizing on recent advances from stretchable and flexible silicon-based devices can lead to a disruption in the electronics for the harsh environments. ...
Monitoring, measuring, and controlling electronic systems in space exploration, automotive industries, downhole oil and gas industries, marine environment, geothermal power plants, etc., require materials and processes that can withstand harsh environments. Such harshness can come from the surrounding temperature, varying pressure, intense radiation, reactive chemicals, humidity, salinity, or a combination of any of these conditions. Here, recent progress in the development of flexible and stretchable electronic devices for harsh‐environment applications is reviewed. Studies are considered on how the selection of a specific material is critical for a particular application and how the selection of the material plays a critical role in sustained performance. Certain examples are presented for selected applications. Works on methods and designs for achieving flexibility and stretchability in devices designed for harsh environments are also investigated. Finally, studies on packaging techniques that enable deployment of conventional electronic devices in harsh‐environment applications are considered, with a few examples described.
... To address these requirements many researchers have reported ideas such as 3-D-stacking of ultrathin chip packages [19], 3-D parallel layer processing [20], and multilayer homogenous integration [8], [20]. In all the above-mentioned cases, the silicon thickness was 10 μm and above [20]- [22]. However, there is always a need to reduce the silicon device thickness, which would significantly impact through-siliconvia (TSV) etch depths; interconnect lengths, and metal/barrier fill requirements. ...
... After completion of the process, some additional process steps are employed to thin down the silicon chip to make it flexible. These include the controlled spalling process [4,5], the trench-protect-etch-release (TPER) process [6,7], and the soft-etch-back (SEB) process [8,9]. ...
... Recently, the discovery of single-crystal Si nanomembranes (SiNMs) has fascinated the flexible electronics community because of their high carrier mobility, stable chemical/thermal properties and flexibility. Particularly, SiNMs released from silicon-on-insulator (SOI) become one of the best choices owing to their outstanding electrical properties, mature fabrication techniques and commercial feasibility at relatively lower cost [10][11][12][13][14]. ...
Bendable single crystal silicon nanomembrane thin film transistors (SiNMs TFTs), employing a simple method which can improve the metal/n-Silicon (Si) contact characteristics by inserting the titanium dioxide (TiO2) interlayer deposited by atomic layer deposition (ALD) at a low temperature (90 °C), are fabricated on ITO/PET flexible substrates. Current-voltage characteristics of titanium (Ti)/insertion layer (IL)/n-Si structures demonstrates that they are typically ohmic contacts. X-ray photoelectron spectroscopy (XPS) results determines that TiO2 is oxygen-vacancies rich, which may dope TiO2 and contribute to a lower resistance. By inserting TiO2 between Ti and n-Si, Ids of bendable single crystal SiNMs TFTs increases 3–10 times than those without the TiO2 insertion layer. The fabricated bendable devices show superior flexible properties. The TFTs, whose electrical properties keeps almost unchanged in 800 cycles bending with a bending radius of 0.75 cm, obtains the durability in bending test. All of the results confirm that it is a promising method to insert the TiO2 interlayer for improving the Metal/n-Si ohmic contact in fabrication of bendable single crystal SiNMs TFTs.
... This has enabled integration of CMOS chips with sensing platforms on PCB or a chip carrier. Recently there has been a lot of research activity on integration of CMOS processed devices in flexible platforms [38], which will enable portable and wearable biosensing LOC diagnostics systems [18], [26], [39]. ...
Scaling by 3-D integration of various heterogeneous components enables miniaturized systems. However, the heterogeneous system integration is challenging due to the dissimilarities in materials and process used in fabrication of individual components. In this paper, we demonstrate a simple 3-D integration method for miniaturization of systems. Various components of the system were stacked using SU-8-based planarization and epoxy-based bonding. Spacer dielectric (SU-8) was patterned using photolithography for the formation of interconnect vias. Electrical interconnects over the large topography between the layers was formed by the screen printing of silver nanoparticle epoxy. Using this integration technique, we demonstrate a fluorescence-sensing platform consisting of a silicon photodetector, plastic optical filters, commercial LED, and a glass microheater chip. This paper resolves several fabrication challenges of planarization, stacking, and interconnection of these divergent chips. For example, the process incompatibility of the plastic optical filters was resolved by additional passivation using parylene-C. The functionality of the demonstrated system is verified by detecting the fluorescence property of Rhodamine B and Rhodamine 6G dyes. Rhodamine B's sensitivity to temperature was also demonstrated using the on-chip microheater. This process flow can be scaled to stack a larger number of layers for demonstrations of more complicated systems with enhanced functionality and applications. [2018-0064]
... Recently, the hydrothermal process gets more attention and well reported for the growth of piezoelectric/ferroelectric films, because of cost-effectiveness, eco-friendly nature, low processing temperature and nanomaterials shape controlling and suitable to use organically printed circuit boards during the synthesis process. Many researchers investigated the growth and functional properties of nanostructured materials on non-flexible substrates are SrTiO 3 [10,11], MgO [12], glass [3], LaAlO 3 [13], and flexible substrates are Ni/Cr metal foil [14], Ti/ Al/Kapton [15], indium tin oxide/polyethylene terephthalate (ITO/ PET) [16,17], silicon [18] and carbon fiber [19], respectively. ...
... The piezoelectric behavior of BTO wire obtained by the electrical responses from the flexible wire based piezoelectric nanogenerator (FW-PNG) upon periodic mechanical force. For real-time utility, demonstrated the possibility of self-powered wire based UV sensor (SPW-UV sensor) using the parallel connection between FW-PNG device and TW-UV sensor under various light intensities (18,40 and 60 mW/ cm 2 ) of the light source (365 nm). ...
A flexible, non-planar, human hair sized [Diameter (Ø) ≈100 μm, Length (L) ≤6 cm] Ti-wire/BaTiO3 (BTO) core-shell nanostructures (NSs) was developed using chemical oxidation-modification (COM) method followed by a low-temperature hydrothermal technique. COM method of flexible/non-flexible Ti-wires (Ø ≈ 800 μm, 100 μm) outer surface generates uniform distribution/continuous radial growth of TiO2 nanoneedles/nanoparticles having anatase crystalline phase. Photo-responsive performance investigated by fabricating the TiO2 NSs/Ti wire (TW) based UV sensors as a function of fixed bias voltages (±1 V and ±7 V) under various light sources having wavelengths (λ) 365 nm, 405 nm and 535 nm. TW-UV sensor (Ø ≈ 800 μm) has higher photo-responsivity ≈35.024 μA/W than the TW-UV sensor (Ø ≈ 100 μm) under the light intensity ≈18 mW/cm² (λ ≈ 365 nm) at bias voltage ≈−1 V, respectively. Further, the XPS spectra of the tetragonal crystalline phase of radially grown BTO NSs confirms the presence of Ba 2+ and Ti +4 oxidation states directly connected to the internal stresses of TiO6 octahedron in BTO lattice. Next, flexible wire based piezoelectric nanogenerator (FW-PNG) was fabricated to harness the mechanical energy, biomechanical motions into useful electrical energy. Realized self-powered UV sensor by the parallel connection between FW-PNG and TW-UV sensor as a function of constant mechanical load (2 N) under various light intensities (18, 40 and 60 mW/cm²) of source wavelength 365 nm, respectively. This study can pave the way for developing micro/nanodevices on non-planar mechanical structures; human hair sized energy harvesters and self-powered sensors.
... Some of ultra-thin CMOS inverters reported in the literature are summarized in Table VI. 186,[188][189][190][191] Only few of them have investigated the effect of bending stress on the performance. The performance of the thinned Si CMOS inverter circuit by Kino et al. 191 degrades under bending stress, as shown in Fig. 11(a) with MOSFET currents and CMOS inverter switching behaviors. ...
... Thus, local bending stress induced stress affects the CMOS inverter, leading to the circuit performance fluctuations in the Si chip. Another example by Sevilla et al. 189 reports thin (40 lm) and flexible (1.5 cm bending radius) Si based functional CMOS inverters whose characteristics show reduced performance for bending radii higher than 1.5 cm as shown in Figs. 11(c) and 11(d). ...
Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.
... 1-4 Flexible devices based on a sc-Si membrane have outperformed the devices relying on conventional organic/amorphous thin films or two-dimensional transition metal dichalcogenides (TMDs). [5][6][7] Ultra-thin sc-Si membranes are often transferred onto polymer substrates to enhance the mechanical stability of the devices. 4,5 Indeed, polymer substrates work well as mechanical support layers for ultra-thin sc-Si membrane flexible devices. ...
Ultra-thin single-crystalline Si membrane transistors on a polymer substrate have drawn attention for flexible electronics applications. However, these devices accompany a reliability issue stemming from severe self-heating because of the inherent poor thermal conductivity of the polymer substrate. In the present study, under an operational condition of VG = 3 V and VD = 8 V, the temperature of the Si membrane transistor on the polymer substrate soared to about 64 °C immediately and remained consistently high. The excess heat generated from the active channel significantly degraded the device performance. However, the implementation of a silver heat spreading layer (HSL) between the active channel and the polymer substrate significantly alleviated the self-heating effect as the silverfilm rapidly spread the generated heat. The efficient heat spreading, monitored via a high resolution infrared thermal microscope, correlated well with the charge transfer characteristics of the device. These results may be helpful to realize high performance flexible devices using a silicon membrane.
