Figure - available from: Journal of Micromechanics and Microengineering
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(a) Stiction force correlation with contact resistance (R DS) extracted from a range of cantilevers with various widths (spring constants). Low contact resistance means a larger actual contact area, leading to higher stiction force. (b) The correlation of stiction force with current conduction through the contact. A higher current flow leads to higher stiction force. The error bars show the standard deviation of the stiction force for an I DS, measured over a number of samples with different widths and G–S gaps but with fixed thickness and D–S gaps.
Source publication
We measure the stiction force using in-plane electrostatically actuated Si nanoelectromechanical cantilever relays with Pt contacts. The average current-dependent values of the stiction force, ranging from 60 nN to 265 nN, were extracted using the I DS vs V GS hysteresis curves, the cantilever displacement information from finite element method (Co...
Citations
... This can be problematic for certain applications. Many types of MEMS devices rely on the Bosch process for fabrication, but some of these devices [12], [13], [14] . However, the optimized Bosch process provides a sidewall roughness of 110 -140 nm peak-to-peak range with a 10 nm RMS deviation, as reported. ...
Cryogenic deep reactive ion etching (Cryo DRIE) of silicon has become an enticing but challenging process utilized in front-end fabrication for the semiconductor industry. This method, compared to the Bosch process, yields vertical etch profiles with smoother sidewalls not subjected to scalloping, which are desired for many microelectromechanical systems (MEMS) applications. Smoother sidewalls enhance electrical contact by ensuring more conformal and uniform sidewall coverage, thereby increasing the effective contact area without altering contact dimensions. The versatility of the Cryo DRIE process allows for customization of the etch profiles by adjusting key process parameters such as table temperature, O2 percentage of the total gas flow rate (O2 + SF6), RF bias power and process pressure. In this work, we undertake a comprehensive study of the effects of Cryo DRIE process parameters on the trench profiles in the structures used to define cantilevers in MEMS devices. Experiments were performed with an Oxford PlasmaPro 100 Estrelas ICP-RIE system using positive photoresist SPR-955 as a mask material. Our findings demonstrate significant influences on the sidewall angle, etch rate and trench shape due to these parameter modifications. Varying the table temperature between −80 °C and −120 °C under a constant process pressure of 10 mTorr changes the etch rate from 3 to 4 μm min⁻¹, while sidewall angle changes by ∼2°, from positive (<90° relative to the Si surface) to negative (>90° relative to the Si surface) tapering. Altering the O2 flow rate with constant SF6 flow results in a notable 10° shift in sidewall tapering. Furthermore, SPR-955 photoresist masks provide selectivity of 46:1 with respect to Si and facilitates the fabrication of MEMS devices with precise dimension control ranging from 1 to 100 μm for etching depths up to 42 μm using Cryo DRIE. Understanding the influence of each parameter is crucial for optimizing MEMS device fabrication.
... Micro-and nano-electromechanical systems (M/NEMS) devices benefiting from the advanced micro/nanofabrication methods exhibit vast potential across numerous application fields, including gas sensors [1], accelerometers [2], and dielectric barrier discharge actuators [1] to name a few. * Author to whom any correspondence should be addressed. ...
... Besides these applications, M/NEMS based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments such as nuclear reactors, particle accelerators, and satellites where conditions make the use of electronics non-ideal [2,3]. In addition to fixed electrodes with sub-micron separations, these devices commonly incorporate flexible electrodes with even narrower controllable gaps from few 100 s to 10 s of nm down to zero nm to facilitate their operation [2,[4][5][6]. ...
... Besides these applications, M/NEMS based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments such as nuclear reactors, particle accelerators, and satellites where conditions make the use of electronics non-ideal [2,3]. In addition to fixed electrodes with sub-micron separations, these devices commonly incorporate flexible electrodes with even narrower controllable gaps from few 100 s to 10 s of nm down to zero nm to facilitate their operation [2,[4][5][6]. In M/NEMS devices, electrostatic forces are usually harnessed to drive mechanical action. ...
A thorough understanding of arc discharge mechanism as well as determination of arc discharge voltage at the nanometer scale remains challenging due to the complexities associated with electrode preparation and precisely maintaining nanoscale separations in experiments. This work addresses this challenge through a novel approach by accurately measuring electric breakdown/discharge voltages between Pt-coated Si electrodes with separations ranging from ∼5 nm to 370 nm using a combination of fixed and flexible nano-electrodes while inherently creating an ideal environment to mitigate the effect of mechanical vibrations on the measurement results. For separations of 10, 100, and 300 nm, the corresponding discharge voltages are ∼15, 75, and 160 V, respectively, with the apparent electric field for the 10 nm separation exceeding 1.5 GV m⁻¹. The results acquired from the investigated electrode configuration closely resembling the laterally actuated nanoelectromechanical system (NEMS) cantilever relays reveals strong agreement with NEMS relay breakdown characteristics, emphasizing the importance of arc discharge considerations while designing micro/nano electromechanical devices. Furthermore, deliberately applied arc discharge is shown to provide electrode nano-welding for realization of configurable NEMS circuits.
... The proposed method has been found to be an effective solution to avoid stiction and improve reliability of the MEMS switches. Another solution to mitigate the stiction problem in MEMS switches is the use of harder metallic materials [143]. However, use of such materials causes issues of pull-in voltage requirements and switches the speed because of more of a stiffness constant for a harder metal. ...
Micro-Electro-Mechanical System (MEMS) switches have emerged as pivotal components in the realm of miniature electronic devices, promising unprecedented advancements in size, power consumption, and versatility. This literature review paper meticulously examines the key issues and challenges encountered in the development and application of MEMS switches. The comprehensive survey encompasses critical aspects such as material selection, fabrication intricacies, performance metrics including switching time and reliability, and the impact of these switches on diverse technological domains. The review critically analyzes the influence of design parameters, actuation mechanisms, and material properties on the performance of MEMS switches. Additionally, it explores recent advancements, breakthroughs, and innovative solutions proposed by researchers to address these challenges. The synthesis of the existing literature not only elucidates the current state of MEMS switch technology but also paves the way for future research avenues. The findings presented herein serve as a valuable resource for researchers, engineers, and technologists engaged in advancing MEMS switch technology, offering insights into the current landscape and guiding future endeavors in this rapidly evolving field.
... These two gasses flow simultaneously allowing for ion bombardment and sidewall passivation to occur at the same time (this is known as a Pseudo-Bosch process) [15]. This yields a highly anisotropic etch, without the characteristic scalloping of a traditional Bosch process, as seen in Figure 4 [15], [16], [17], [18], [19]. Then, the residual e-beam resist was removed, and the cantilevers were released from the oxide beneath via wet etching of the exposed oxide layer in 49% hydrofluoric acid for 2 min. ...
... This conventional technique results in a conformal sidewall coating as confirmed by SEM imaging and electrical testing. The fabrication process, depicted in Figure 4, allows for the robust construction of relays without requiring multiple lithography steps as is the case with vertically actuated relays [19]. A target pull-in voltage of 60 V was chosen for control circuitry applications; however, this value can be tuned by varying the device dimensions [7], [19]. ...
... The fabrication process, depicted in Figure 4, allows for the robust construction of relays without requiring multiple lithography steps as is the case with vertically actuated relays [19]. A target pull-in voltage of 60 V was chosen for control circuitry applications; however, this value can be tuned by varying the device dimensions [7], [19]. ...
Nano electro-mechanical systems (NEMS) based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments where conditions make the use of electronics non-ideal. The principal advantages of NEMS are the inherent near zero leakage current and ability to operate in harsh conditions where substantial parasitic field effects are present. In this work, we design and experimentally demonstrate NEMS based logic gates which utilize multi-gate relays, designed to actuate when input signals are applied to all gate terminals simultaneously. This design enables signal propagation through a single relay for NAND, NOR, and NOT gates with any number of inputs, eliminating variations of output resistance and capacitance, which affect the output generation time. Furthermore, these devices are fabricated using a conventional process requiring only one lithography step. These devices can be utilized to produce all primary logic functions. The proposed platform exclusively uses relay structures based on straight cantilevers, favoring a complementary logic, and allowing for the aforementioned improvements over current designs. The relay structures are optimized using a procedure based on COMSOL simulations. The efficacy of the logic gate designs, and corresponding optimization procedures are validated through a series of electrical tests on fabricated 3-input NAND gate structures utilizing a multi-gate relay. The tests show successful operation for input voltages ranging from 62 and 74 V thus confirming that the approach put forth in this paper can effectively constitute NEMS based complementary logic circuits, while fulfilling all constituent input and output requirements. 2023-0125
Nano/microelectromechanical systems (N/MEMS) based complementary logic circuits offer a physically robust alternative to conventional CMOS control systems, which are able to function in environments unsuitable for transistor devices. In this work we demonstrate novel, configurable, complementary logic circuits comprised entirely of relays at both NEMS and MEMS scale, which are capable of fulfilling all primary logic functions. Lifetime testing of the fabricated devices revealed two key failure modes: contact degradation and welding of high voltage cantilevers, both of which are caused by the charging and discharging of unwanted parasitic capacitances inherent to complementary relay structures. Devices are consequently damaged by high transient current and arc discharge between contacts. Several solutions are proposed and implemented to mitigate these issues, including minimization of unwanted capacitances, optimization of metallization scheme, introduction of intermediate operation cycles intended to increase time between state changes, and prevention of welding by preemptively charging capacitors to an intermediate voltage. To this effect, a detailed study of lifetimes for both single cantilevers and logic gate structures is presented comparing a variety of metallization schemes using Pt, Ti, TiN, and W, including their multilayer combinations. These varied optimization methods yielded single cantilever lifetimes of 1.74 billion cycles on average for devices with a Ti adhesion layer, a Pt primary layer, and a W surface layer to increase durability. Using the same metallization scheme, complementary logic structures achieved 0.6 million cycles on average. These results demonstrate the viability of robust N/MEMS based complementary logic circuits for safety critical control applications. 2024-0203
