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In the applications of 3-D packages or stacked die packages, mostly the silicon wafers have to be ground thinner, and then the strengths of the dies from the wafers are needed for assuring good design and reliability of the packages. The purposes of this study are twofold: one is to attempt to develop a new, suitable test method for differentiating...
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This thesis is on the subject of millimeter-wave frequencies (from 30 to 300 GHz) packaging of integrated circuits. Potential applications are radar imaging and security applications as well as TRX (transmission and reception) modules for 5G base stations to give some examples. For these applications, integrated circuits are now available from the...
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... To effectively compare the reliability of the fabricated dummy chips, we measured the die strength using a three-point bending test, G86-0303, following the Semiconductor Equipment and Materials International (SEMI) standard [21][22][23][24][25][26][27]. The three-point bending test is commonly employed to examine the effects of shape, surface treatment, and die geometry on die strength for large and deep cracks generated during the wafer-thinning process based on linear beam theory [3,12]. ...
The demand for advanced packaging is driven by the need for low-profile, densely-integrated, large-die Si devices in substrate-based or wafer-level packaging. Die strength is a critical parameter for ultrathin dies, making die singulation a vital aspect of advanced packaging technology. In this work, we present a dicing before grinding (DBG) process to compare and analyze die strengths using a mechanical blade, stealth laser, and plasma dicing. The three DBG processes were applied to a 200 mm silicon (Si) wafer process with a die size of 10 × 10 mm ² and thicknesses of 100, 200, and 300 μm, respectively. Optical and electron microscopes were employed to investigate chipping quality, sidewall damage, and surface contamination. The bare Si die’s strength was assessed using a three-point bending test. Plasma dicing before grinding (PDBG) resulted in less contamination, chipping, and cracking compared to other DBG processes. Furthermore, PDBG exhibited the highest die strength of 1052 Pa.
... To solve the problem, some giant mobile companies have started to apply flexural bending test, such as three-point bending test (3PB), onto electronic packages, and further set the strain value as the package strength gating criteria. In industry or academics, the idea of using flexural bending to evaluate the mechanical performance , is widely discussed and adopted in the die-level for die strength testing only [11][12][13][14][15][16][17][18][19][20]. Even there are few studies and standards regard with the package-level mechanical test, some mobile system companies, IC manufacturing plants , and IC testing sites have started to access package mechanical performance through flexural bending test. ...
In mobile market, the demand of memory packaging increase year over year. While the form factor of memory packages moves toward smaller and thinner geometry with higher pin counts, the package overall mechanical robustness becomes one of a key criteria for mobile companies regarding to consumer usage condition. Package strength is an indicator for package robustness. Package with low strength may likely lead to die cracking or epoxy mold compound (EMC) cracking during assembly, testing, reliability testing or consumer field usage. In this study, comprehensive factors will be covered to discuss the impact on package strength performance. In addition, the failure analysis would be studied aiming to observe initial crack point. Last, the study will discuss about the current testing methodology and will later propose new testing methodologies which are more suitable to field application condition.
... There are also many criteria to judge the quality of dicing saw processing, such as the maximum chipping width generated by the scribing process [3], the maximum chipping area, and the width of the cutter marks. If the maximum chipping width is too wide, the internal circuitry of the workpiece will be damaged and the workpiece will be directly scrapped and unusable [4,5] Therefore, in this paper, the maximum chipping width is used as the index for judging the cutting quality. ...
Wafer dicing saw is one of the core equipment in the manufacturing process of semiconductor integrated circuit components. The cutting accuracy of dicing saw directly affects the overall quality of processed chips. This paper systematically investigates the relationship between the main cutting process parameters and the cutting quality of the dicing saw. The orthogonal experimental design method and genetic algorithm are used to optimize the cutting process parameters, solving the high cost and low efficiency problems caused by the traditional way of selecting parameters by trial and error. After optimization, the average maximum chipping width is only 38.54 μm, which is 8.23% better than the traditional way of cutting quality. Based on the blade thickness of 35 μm, the maximum chipping width reached the industry-recognized best standard of 1.1 times the blade thickness, further proving the effectiveness of the method.
Article Highlights The first joint application of orthogonal regression design method and evoluti-onary algorithm for parameter optimiza-tion of dicing saw.
A set of optimal cutting parameters are found and verified by experiments.
Compare and contrast the optimal cutting parameters cutting’s performance.
... Thus, the determination of bending strength of silicon dies is of importance for package designs. Among the test methods of determining the die strength, the three-point bending test with a uniaxial bending nature has been extensively applied [6][7][8]. The issues of free edge stress [9] and geometric nonlinearity [10][11][12] on the three-point bending strength have been extensively studied. ...
... The nonlinear-effect correction of the average strength for 110 lm-thick specimens is more apparent than that for 160 lm-thick specimens, due to the thinner specimen experiencing nonlinearity more severely as shown in Fig. 8. The typical failure mode also shows the dominant cracks in the [110] crystallographic directions, rather than in radial direction, attributable to the existence of the weaker planes [8], even though the loading is axisymmetric. For a statistical plot, both theory and NFEM-converted strength data are replotted in Fig. 23 by Weibull distribution. ...
... (2) associated with Eqs. (8) and (9)) is only limited to the linear failure stress in the BoR test for relatively thick dies, while the NFEM solution (listed in Table 2) can provide both linear and nonlinear failure stresses, especially for testing the relatively thin dies. ...
The ball-on-ring (BoR) test, one of the most popular biaxial bending tests, is thoroughly investigated in this study for determining the bending strength of thin silicon dies. The application of this test method with a linear theory to the thin dies is also reevaluated using a nonlinear finite element method (NFEM) by taking into account the geometric nonlinearities, including large-deflection (global) and contact (local) nonlinearities. Mechanics of the BoR test is also discussed in terms of geometric linearity and nonlinearity. It is found that the bending strength calculated by the existing linear theory for the BoR test is still valid for the non-thin die specimens, but not for thin ones. The reason is that the thin-die specimens in the test suffer a contact-nonlinearity effect, due to a maximum applied stress moving away from the loading pin center during the loading process. The global geometric nonlinear (large-deflection) behavior occurring in the three-point bending test is not observed in the test. For applications, the fitting equations of the maximum stress in terms of applied load are proposed based on the NFEM results. Those fitting equations only depend on the specimen thickness, the head radius of the loading pin, and the elastic modulus of the specimen, but not on the specimen radius, a supporting ring radius and the head radius of the ring. The 110 µm and 160 µm-thick silicon dies in the BoR test are also demonstrated with the related fitting equations.
... Indeed, during their operation lifetime packaged die, intended e.g. for automotive and industrial applications, undergo remarkable thermal cycles, which unleash mechanical stresses. The accidental presence or generation of cracks [6] [7] can compromise the operating life of a device missing the strict qualification standards for the packages that must be complied within the automotive industry (e.g. AEC-Q 101). ...
The paper reports the mechanical properties of 4H-SiC die with different thicknesses, that have been determined through a 3-point bending (3-PB) test. In particular, it reports 1) the measurement of the failure strength of thin 4H-SiC rectangular die; 2) the Weibull analysis of the failure strength of 4H-SiC die, exploited to determine the maximal load that can be applied to the die, without any breakage; 3) the measure of 244±15 GPa for the flexural Young modulus E of SiC die, gained from the 3-PB test elaborations.
... Therefore, the determination of thin die bending strength is very important for package designs and reliability. Among the test methods of determining the die strength, the three-point bending test with a uniaxial bending nature is widely used [6]- [8]. The effects of free edge stress [9] and geometric nonlinearity [10]- [12] on the three-point bending strength have been thoroughly investigated recently. ...
The easy-to-use point-load on elastic foundation (PoEF) test, similar (or alternative) to a typical biaxial bending ball-on-ring test, is studied for determining the bending strength of thin silicon dies. The feasibility of this test method with a linear theory is also evaluated using a nonlinear finite element method (NFEM) by taking into account geometric and contact nonlinearities. The mechanics of the PoEF test is discussed in terms of geometric linearity and nonlinearity. The results show that the geometric nonlinearity would cause significant errors of bending strength data, due to the maximum applied stress moving away from the loading pin center, if the linear theory is applied for thin die specimens in this test. The comprehensive fitting equations based on the NFEM results, with better accuracy than the linear theory, are proposed for calculating the thin die strength. Some key parameters, including the head radius of the loading pin (
${r}$
), elastic modulus of the foundation (
$E_{EF}$
), elastic modulus of the test specimen (
${E}$
), and test specimen thickness (
${t}$
), are also discussed individually by studying their effects on the fitting equations. In an experimental implementation, the thin silicon die specimens with various thicknesses are actually performed in the PoEF test. It is found that the thinner specimen suffers from more severe geometric nonlinearity effect. The statistical strength data converted by the fitting equations are demonstrated and show that the geometric nonlinearity has to be taken into account in the PoEF test when the thin specimens are tested. The ready-to-use fitting equations proposed in this study are proved to be viable solutions for the conversion of those nonlinear test data.
... Therefore, in-situ determination of thin die bending strength data is very important for package designs. Among the methods of determining the die strength, the three-point bending test is widely used [5][6][7]. Most recently, the effect of edge stress during the three-point bending test on the bending strength has been closely investigated [8]. ...
With the trends of electronic packaging development toward small size, low-profile features, high-pin count, and high performance, the 3D IC (Three-dimensional Integrated Circuits) or stacked-die packages have been gaining popularity. For such package applications, IC silicon wafers have to be ground and processed to be relatively thin and then the thin silicon dies cut from these wafers have to gain sufficient strength in order to bear high stresses resulting from process handling, reliability testing, and operations. Hence, the strength of the thin dies has to be determined to ensure the good reliability of the packages. Three-point bending test is commonly used for measuring die strength; however, the feasibility of the test is still questionable for determining the strength of relatively thin dies. Therefore, the feasibility of the linear beam theory is evaluated by a nonlinear finite element method (NFEM) with taking into account geometric nonlinearity in this study. The results show that this nonlinearity would cause errors of the strength of thin dies if calculated by the linear beam theory. The fitting equations of the correction factors (η) to linear solutions, extracted from the NFEM simulation, are proposed and proved to be workable with very good accuracy. It is also found that the correction factor highly depends on the deflection (δ), span length (L) and radius of roller support (r), but not elastic modulus (E) and thickness (t) of test specimens. After the nonlinearity has to be taken into account for the relatively thin silicon dies, the consistent statistical strength data have been obtained for various thicknesses of the test die specimens.
... However, sawing might result in chipping on the front and back sides of a wafer [7,8] conditioned by the wafer material, grain size, rotation, and feed rate [9]. These defects might lead to the die's operational loss both immediately after cutting and in the course of the device operation [10][11][12][13]. ...
When a silicon wafer is cut into separate dies, their front and back sides might have chipping resulting in die cracks and yield loss. To prevent defect formation, silicon wafers should undergo optical inspection for evaluation of wafer chipping, its size, and its shape. This work proposes an automated method of image processing that includes die edge detection, die street search, and determination of chipping size and shape. Die edge search was done using an Otsu’s thresholding method. This technique was chosen out as the optimal of the five ones. The choice was based on the segmentation precision evaluation of two types of images: with sharp and blurred edges. Die street search was done using a developed algorithm capable of processing images with angular displacement. Chipping shape and size were calculated through die edge displacement from the die street. Based on the numerical evaluation of chipping size and shape, a chipping danger metric that may be used for detection of defective dies has been proposed.
... Typical values of silicon die strengths are in the range 300-700 MPa (e.g. [18,19]). ...
The reliability of a photodiode module intended for operation at 4. K was investigated. Flip-chip bonded photodiodes and an adhesively bonded optical fiber attachment structure were considered. Finite element simulations of the thermomechanical stress were used to evaluate the stresses in different design configurations. Results showed that issues with chip cracking in silicon were eliminated by proper selection of component materials. Photodiode modules survived thermal cycling to 77. K and extended operation in 4. K.
... See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. proposed for investigating silicon die strength [17] and later thin Cu-TSV memory dies [18]. An acoustic emission (AE) method was for the first time used in detecting initial crack silicon die during the compression test [19]. ...
The 2.5D IC packaging technology is to apply a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform to interconnect and integrate heterogeneous and homogeneous chips horizontally and vertically. The existing Cu TSVs might make the silicon interposers more fragile, due to their structural non-homogeneity and weak interfaces. Thus, the strength determination of silicon interposers becomes one of important issues for ensuring reliability of 2.5D packages. This study aims to determine the bending strengths of silicon interposers (with back-side and front-side surface controls—corresponding to the surfaces with C4 bumps and Cu/SiO2 layers, respectively) using a point-load-on-elastic-foundation (PoEF) test, associated with an acoustic emission (AE) method of detecting local material cracks or delamination occurring during the test before the interposer breaking. The results indicate that there are a few less-than-50 dB AE signals occurring before the interposer breaking, due to the micropad crush on the Cu/SiO2 layer induced by the loading-pin contact, for the back-side control case, but not for the front-side control case. In addition, the interposer breaking is found to be triggered by the maximum tensile stresses located at the corner of C4 bump pad for back-side control case, instead of micropad crush or Cu TSVs, while at silicon or Cu/SiO2 layer for front-side control case. These failure behaviors have been confirmed by theory-validated finite element simulation. The bending strengths of silicon interposers have further been determined by using experimental data associated with a finite element analysis by taking into account Cu material nonlinear properties and the Cu/SiO2 layer.