Vdd vs. SVNM. 

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... read current flows through the storage node directly, thereby causing read disturbance , i.e. , the voltage at data node Q will rise temporarily. This will degrade the read stability because the cell flipping will be more likely to take place. The pull-up transistors P1 and P2 are usually made weaker for easy write operation just like in a conventional 6T cell. While the pull-down transistors ND1 and ND2, forming the cell discharging paths, need to be stronger to facilitate a larger read current and thereby a quicker access. The pass gate transistors NA1 and NA2 need to be strong enough to serve as high-conduction paths between the accessed cell and the bitlines during both the read and write operations. The two pull-up transistors, PP2 and PP3, need to be slightly stronger, to compensate for the conductivity degradation of the cascaded PMOS structure linking the storage nodes ( i.e. , Q and Qb) and Vdd, which help contribute to a good hold SNM. Unlike a 6T cell, the pull-down transistors do not have to be strong, since they do not involve in the cell discharging paths. However, their strengths are made comparable to the cascaded PMOS structure mentioned above to ach- ieve a more balanced cell structure which could lead to a larger hold SNM. In our cell we have seen that the SVNM has been 1.53times greater than that of conventional 6T cell. In our cell we achieved 460mv while for 6T it is 300 mv. The leakage power has also been reduced by 3.3 times than that of conventional 6T. Numerous analytical models of the static noise margin (SNM) have been developed to optimize the cell design, to predict the effect of parameter changes on the SNM and to assess the impact of intrinsic parameter variations on the cell stability. Furthermore, new SRAM cell circuit designs have been developed to maximize the cell stability for future technology nodes [8]. The set up for N curve is as shown in Figure 3 . In an ideal case, each of the two cross-coupled inverters in the SRAM cell has an infinite gain. As a result, the butterfly curves delimit a maximal square side of maximum, being an asymptotical limit for the SNM. Therefore, scaling limits the stability of the cell. An additional drawback of the SNM is the inability to measure the SNM with automatic inline testers [4], due to the fact that after measuring the butterfly curves of the cell the static current noise margin (SINM) still has to be derived by mathematical manipulation of the measured data. An alternative definition for the SRAM read stability is based on the N-curve of the [5]. N-curve contains information both on the read stability and on the write- ability, thus allowing a complete functional analysis of the SRAM cell with only one N-curve [8]. Parameters which are find by using N curve these 4 parameters are useful for measuring the write ability and read ability of the cell.  The static voltage noise margin ( SVNM ) The static voltage noise margin is the voltage difference between points A and B in Figure 4 and it indicates the maximum tolerable DC noise voltage at the input of the inverter of the cell before its content changes [4].  The static current noise margin ( SINM ) The static current noise margin is defined as the maxi- mum value of DC current that can be injected in the SRAM cell before its content changes [4]. It is given by the peak value of Iin during read operation that is between points A and B in the Figure 4 .  The Write Trip Voltage ( WTV ) The SRAM N-curve also provides information re- garding the write ability of the cell. WTV is the voltage drop needed to flip the internal node “1” of the cell with both the bit lines clamped at Vdd [4]. It is given by the voltage difference between the second (B) and the last zero crossing point (C) in Figure 4 .  The Write Trip Current ( WTI ) It is the amount of current needed to write the cell when both bit lines are clamped at supply voltage equal to Vdd [5]. The peak value of Iin after the second zero crossing of N-curve gives WTI. For better read stability, the values of SVNM, and the magnitude of SINM and hence the value of static power noise margin SPNM (product of mean of SVNM and mean of SINM) should be larger. For better write ability the value of WTV, the absolute value of WTI and hence the value of WTP (product of mean of WTV and mean of WTI) must be smaller. N-curve analysis has been done at 45nm technology in order for low voltage operation. Various factors of stability has been analyses with the affect of temperature and voltage on them. Figure 5 shows one N curve analysis at Vdd = 1 V at temperature varies from –25 ̊ C to 125 ̊ C [2]. We have seen that there is significant affect of power supply on the 4 parameters which we have obtained from the Ncurve.As Vdd increases the stability also increases [9]. This is also been observed here that as the Vdd increased the SINM, WTV, SVNM and WTI the four parameters has been increased as shown in the given graphs. As shown in the graph Figure 6 , we see that at Vdd = 1 V it is maximum 460 mv and reduces when we go to Vdd = 0.6 V. As we know that SVNM it is the maximum DC tolerable voltage before the cell changes it contents so it means that as Vdd reduces the cell tolerance is also reduces. As discussed above the write-trip current (WTI) is the amount of current needed to write the cell when both bit-lines are kept at Vdd . This is the current margin of the cell for which its content changes as in ( Figure 7 ). The ability to write a cell with both bit-lines clamped at results actually in a destructive read operation; therefore, the absolute value of WTI should be large enough to cope with the read stability requirement. On the other hand, the lower the absolute WTI is, the higher the write-trip point of the cell. It shows an exponential rela- tion with Vdd. WTI is measure at various temperatures. Write-trip voltage (WTV) is the voltage drop needed to flip the internal node “1” of the cell with both the bit-lines clamped at Vdd. Write ability requires both WTI and WTV.WTV increases with Vdd. At 1 V the cell has maximum stability and it decreases drastically when the Vdd reaches to 0.6 V. As shown in Figure 8 . By using the combined SVNM and SINM, the read stability criteria for the cell are defined properly. For exam- ple, a small SVNM combined with a large SINM will still result in a stable cell since the amount of required noise charged disturb the cell is large. At Vdd 1V we have good SINM but it reduces exponentially at Vdd = 0.6 V, as shown in Figure 9 . As we have varied the temperature from 0 ̊ C to 125 ̊ C we have seen that the SVNM and WTV is unaffected by the temperature variation but the currents i.e. the write trip current and static noise margin current has been af- fected by temperature variation. As temperature increases both the SINM and WTI reduces. As shown in Figures 10 and 11 respectively. The variation has been observed at varying Vdd from 1 V to 0.6 V. In this cell we have achieved 33% less leakage power with respect to 6T SRAM cell, as in this cell we have used the PMOS cell and also we used ND3 which is used to reduced the leakage power. We have seen the affect of Vdd and temperature on leakage power. As we know it depends exponential to Temperature and increases with temperature the same affect is seen here Figure 12 . It also shows the effect of Vdd which shows that there is 7X increases in Leakage current when we increase the Vdd from 0.6 V to Vdd 1 V. We have also analyzed the Leakage power with SINM as shown in Figure 13 and found that as SINM increases the Leakage power also increases which shows that with increasing Vdd the SINM increases and at the same time increasing Vdd results in increasing the leakage power [10]. We have proposed a novel 9T SRAM cell which has been simulated at 45 nm 65% increase in SVNM compared to 6T SRAM cell. The cell has 33% leakage power reduction also with respect to 6T SRAM cell and in this we have not used any leakage reduction techniques. So the future expansion can be done by sizing the cell to increase the stability i.e . the write ability and read ability of the cell. Also power can be reduced by using various leakage reduction methods. Although the area with respect to 6T has been increased but at lower technology it is comparable to 6T. The SNM measured is 380mv which can be improved by sizing the transistor widths. The authors are very grateful to the respective organiza- tion for their support and ...