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Two states in the coherence protocol.
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This paper presents a case study on the formal specification of a cache coherence protocol and the verification of some of its safety properties. Cache coherence refers to the consistency between the contents of a memory resource shared by many processes, that can have read and write access, and each local copy of the memory contents. The protocol...
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... an example, Figure 1 depicts two states that the protocol can reach. In state (a), process a has exclusive access to the shared resource, while processes b and c are idle (i.e., they have no access or, equivalently, have invalid access to the resource). ...
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Citations
... SystemVerilog's support for Assertions with UVM package can be the right goal to concentrate towards the verification frame for such complex protocols i.e. we have done with. We are focused with widely used MESI protocol verification process to reduce time to market through reducing most time consuming verification cycle, achieving architectural verification for MESI coherence [2] protocol and taking functional coverage in formal verification on industry standard verification tools support to SystemVerilog and UVM constructs. ...
Shared memory resources are inevitable components in modern SOC architecture due to Multi-core Architectures resulting ease synchronization with enhanced speed and reliability. Again architectural verification are challenging for these protocols for coherency systems. Hence this project work has come out with complete verification environment for such a complex MESI coherency protocol based on model checking and assumes guarantee verification methods developed through compositional approach of SystemVerilog Assertions (SVA) with functional verification using Universal Verification Methodologies (UVM) packages to substantially ameliorate the difficulties for design accuracy.
... Cache coherence protocols can be formally specified as automata and verified by (parametrised) model checking (e.g., [9,25,27]) in terms of operational formalisations which abstract from the specific number of cores to prove the correctness of the protocols (e.g., [10,11,34]). For example, Maude's model checker has recently been used to verify the correctness of configurations of the MSI and ESI protocols [20,28]. In contrast, our work, which also uses MSI, focuses on specifying the abstract interactions between caches and shared memory for parallel programs executing on a multicore architecture. ...
On shared memory multicore architectures, cache memory is used to accelerate program execution by providing quick access to recently used data, but enables multiple copies of data to co-exist during execution. Although cache coherence protocols ensure that cores do not access stale data, the organisation of data in memory and the scheduling of tasks may significantly influence the performance of a parallel program in this setting. As a step towards understanding how the data organisation impacts the performance of a given parallel program using shared memory, this paper proposes a framework defined in Maude for the executable modelling of program execution on cache coherent multicore architectures, formalising the interactions between cores executing tasks, their caches, and main memory. The framework allows the specification and comparison of program execution with different design choices for the underlying hardware architecture, such as the number of cores, the data layout in main memory, and the cache associativity.
The performance of software running on parallel or distributed architectures can be severely affected by the location of data. In shared memory multicore architectures, data movement between caches and main memory is driven by data accesses from tasks executing in parallel on different cores and by a protocol to ensure cache coherence. This paper integrates cache coherence in a formal model of data access, to capture such data movement from an application perspective. We develop an executable model which captures cache coherent data movement between different cache levels and main memory, for software described by task-level data access patterns. The proposed model is generic in the number of cache levels and cores, and abstracts from the concrete communication medium. We show that the model guarantees expected correctness properties for cache coherence, in particular data consistency. This paper further presents a proof-of-concept implementation of the proposed model in rewriting logic, which allows different choices for the underlying hardware architecture of dynamically created parallel data access patterns to be specified and compared at the modelling level.
The performance of software running on parallel or distributed architectures can be severely affected by the location of data. On shared memory multicore architectures, data movement between caches and main memory is driven by tasks executing in parallel on different cores and by a protocol to ensure cache coherence, such as MSI. This paper integrates MSI in a formal model to capture such data movement from an application perspective. We develop an executable model which integrates cache coherent data movement between different cache levels and main memory, for software described by task-level data access patterns. The proposed model is generic in the number of cache levels and cores, and abstracts from the concrete communication medium. We show that the model guarantees expected correctness properties for the MSI protocol, in particular data consistency. This paper further presents a proof of concept implementation of the proposed model in rewriting logic, which allows different choices for a program’s underlying hardware architecture to be specified and compared.
This work reports an effective design of protocol processor (PP), the key component of coherence controller, in a Chip Multiprocessors (CMPs) cache system. It caters to the need for determining the state of a data block in processors' private caches with high accuracy. An insignificant defect in the PP can introduce major inconsistencies in computing the states of cached copies of a data block. A realizable PP, therefore, is a necessity for accurate computation of cache line states. The proposed design is the outcome of radical change in the design approach of PP. The modeling tool of cellular automata (CA) is considered for the design. The special class of cellular automata with single length cycle attractors (SLCA) is tuned to replicate the PP for computing cache line states in CMPs. Theory has been developed to empower the SLCA based PP to sense its malfunctioning and that leads to the design of a self-correcting PP.
