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Trends for wafer thickness, wafer diameter, and die thickness. (Ó S. Savastiouk. Reproduced with permission from S. Savastiouk. 10 Permission to reuse must be obtained from the rightsholder.)
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Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As th...
Citations
... Integrated circuits play a crucial role in modern production and daily life, and their manufacturing process is complex and precise. Even slight changes in materials, environments, and process parameters can result in numerous wafer defects [1][2][3][4]. As a vital step in production, timely wafer defect detection is essential for improving chip productivity and yield [5][6][7]. ...
... In addition, we set up dedicated threads for the weight calculation module and load information collection module to ensure that each module can work independently. Meanwhile, we set the end flag endflag and the weight update flag wtflag to false (lines [1][2][3][4][5], indicating that the current task scheduling has not ended and the weight value does not need to be adjusted temporarily. Then, load-balancing scheduling (lines 7-16) is performed under the framework of SWRR, and the results of each scheduling are recorded in the sequence. ...
The increasing wafer yield and shrinking size pose challenges for real-time defect inspection using a single computer. To address this, we propose enhancing real-time performance by increasing computing devices. However, uneven load distribution due to device performance or defects variations can reduce inspection efficiency. We introduce computer cluster load balancing to solve this, utilizing a load-balancing model and an objective function. We propose the adaptive discrete quantum particle swarm optimization algorithm (ADQPSO) for efficient load balancing and implement the adaptive dynamic smooth weighted round-robin algorithm based on ADQPSO. Experimental results demonstrate that our algorithm achieves the fastest execution speed and up to a 24% improvement in performance. Our approach significantly improves real-time performance and efficiency in wafer surface defect inspection.
... Normally, fly cutting or ultra-precision turning was usually applied to achieve high parallelism [7][8][9]. Nevertheless, the two surfaces of the workpiece are cut in turn during machining, and only the total thickness variation (TTV) can be guaranteed. The flatness as well as the parallelism cannot be improved, owing to the weak rigidity, which would cause deformation by the residual stress [10][11][12]. ...
Double-sided lapping (DSL) is a precision process widely used for machining flat workpieces, such as optical windows, wafers, and brake pads owing to its high efficiency and parallelism. However, the mechanism of parallelism error reduced by the DSL process was rarely investigated. Furthermore, the relationship between parallelism and the flatness was not clearly illustrated. To explain why the parallelism of workpieces becomes convergent by the DSL, a theoretical model has been developed in this paper by calculating the parallelism evolution with the consideration of variation contact situations between workpieces and lapping plates for the first time. Moreover, several workpieces, including a slanted one rendering the model close to the actual process, are taken to calculate the parallelism evolution, and the mechanism of the parallelism error reduced by the DSL process is clarified. The calculation result has indicated that the parallelism error was reduced from 100.0 μm to 25.6 μm based on the parallelism evolution model. The experimental results showed that the parallelism improved from 108.6 μm to 28.2 μm, which agreed with the theoretical results well.
... Non-modification polishing refers to the removal of the workpiece material without material modification. Unlike other classification approaches (compliant and conventional polishing [51], dry and wet polishing [52], etc.), this classification is proposed to realize ACS efficiently on complex surfaces, namely freeform surfaces by serially combined processes of chemical modification polishing and non-modification polishing, as shown in Figure 3. ...
Roughness down to atomic and close-to-atomic scale is receiving an increasing attention in recent studies of manufacturing development, which can be realized by high-precision polishing processes. This review presents polishing approaches at atomic and close-to-atomic scale on planar and curved surfaces, including chemical mechanical polishing, plasma-assisted polishing, catalyst-referred etching, bonnet polishing, elastic emission machining, ion beam figuring, magnetorheological finishing, and fluid jet polishing. These polishing approaches are discussed in detail in terms of removal mechanisms, polishing systems, and industrial applications. The authors also offer perspectives for future studies to address existing and potential challenges and promote technological progress.
... The technology has existed since the early days of the semiconductor industry and is a matured process, with complex saw blade designs, materials, and process recipes [10]. Blade dicing has a cutting mechanism similar to grinding in which material is sheared away from a wafer by fine abrasive particles embedded on the edge of a rotary blade [11,12]. The dicing blade acts as a thin grinding wheel which is rotated at a high speed to grind the wafer resulting in a full or partial cut through the wafer thickness. ...
... The dicing blade acts as a thin grinding wheel which is rotated at a high speed to grind the wafer resulting in a full or partial cut through the wafer thickness. As the wafer thickness decreases below 100 μm, blade dicing tends to cause serious wafer damage such as chippage, cracks, delamination, and residual stress in the singulated dies and hence drastically reducing the process yield [11][12][13][14][15]. This becomes a huge challenge with the trend of the semiconductor industry towards ultrathin wafers, defined as wafers having thickness <100 μm [16]. ...
... At the outset of this article, we review previous theoretical and experimental work on laser-material interaction in Si, providing the basis for our review on laser dicing of Si wafers which is the main thrust of this article. With the increasing usage of metal layers, such as Cu on the backside of ultrathin Si wafers for mechanical stabilization against warpage and process-induced damage [12], we also review laser-material interaction in Cu and discuss recent findings on the effects of laser dicing through Si wafer and Cu backside metallization simultaneously on the microstructural and fracture strength properties of the ultrathin die. This review aims to complement the existing reviews in the areas of laser-material interaction and laser cutting by Shirk et al. [7], Cheng et al. [9], Lei et al. [11], and Jiang et al. [28], and subsequently focuses on laser dicing of Si wafers with emphasis on ablation rate, ablation precision and quality, and die fracture strength. ...
Over the last decade, lasers have been gradually employed for Si wafer dicing to replace blade dicing. Laser dicing has the potential to replace blade dicing as the future generation ultrathin wafer singulation method as it enables higher cutting speed, lower damage, and smaller kerf width but various technical challenges still remain to be resolved. In this article, laser ablation and dicing of Si wafers are reviewed in terms of the physics of laser-material interaction based on nanosecond, picosecond, and femtosecond pulse durations. The effects of various laser settings, dicing process parameters, and material factors on ablation rate, ablation precision and quality, and die fracture strength are discussed in detail. With the increasing usage of Cu stabilization layer on the backside of ultrathin Si wafers, we also review laser-material interaction in Cu and elaborate on recent findings on the effects of laser dicing through Si and Cu simultaneously on the microstructural and fracture strength properties of the die. Various approaches to improve the ablation rate, ablation quality, and die fracture strength are discussed.
... Although the fine grinding can remove most of the damage layer introduced by a previous mechanical process, there remains subsurface damages (SSDs) and micro-cracks close to the surface [6]. Additionally, these damages can further cause the degraded mechanical and electrical properties in the final electronic products [7,8]. The quality of the wafer is crucial to improve the functional performance of the incorporated devices. ...
Atmospheric-pressure (AP) plasma sources have attracted researchers in many engineering fields, due to its low cost and easy handling. The AP plasma technique has been successfully applied on the surface figuring and texturing of Si, fused silica, RS-SiC, and SiC, etc. However, these studies focus more on better control for surface figuring of the substrate. The understanding of how the Si surface roughening or smoothing is occurred during the AP plasma etching using He-based CF4 mixture gas has seldom been reported. The present study starts from a parametric study of O2 addition concentration to He-based CF4 plasma. A groove is initially etched on a single-crystal silicon wafer by the CCP-type parallel-plate plasma etcher, to study the etching rate, surface morphology, material removal characteristics, and surface roughness evolution after the plasma etched removal. It is revealed that the material removal with a typical profile is achieved without introducing further damage. At the same time, the surface finish and surface integrity were enhanced by the AP plasma. The underlying mechanism of the process was investigated. Additionally, the optimized gas composition is then applied to the larger area etching by the computer-controlled scanning with different feed rates. Based on the experimental results, the surface evolution during the plasma etching process is revealed in detail. The surface removal profile also demonstrates that this method can provide an alternative way to achieve damage-free material removal for a larger area substrate by the duplicating of the typical removal profile with different etching path.
... Aligned with the trend of smaller and faster transistors, the electronic industry continuously pushes for thinner and larger die with finer bump pitch [1,2]. However, the commonly used mass reflow (MR) process no longer supports such thin and large die with fine bump pitch, and issues such as non-wet bump, bump bridge, and crack of the extremely low-k (ELK) material are observed [3][4][5]. ...
Laser-assisted bonding (LAB) is the next generation flip-chip bonding technology that can overcome the limitations of the mass reflow process. The heating mechanism of the LAB process is based on the absorption of the laser's energy by a target material. Previous research reported the reflectance (R), transmittance (T), and absorbance (A) spectra of a silicon sample, which are crucial data for determining the laser parameter, such as power and emission time. The present study reports the equivalent data for a silicon sample with a backside metallization layer. The test vehicle was successfully bonded by optimizing the laser parameter, in special the laser power. The results reported on this research confirms the feasibility of the LAB process for a flip-chip die with backside metallization.
... Based on the technical progress and development, these components continue to get smaller and thinner, allowing for improved heat dissipation, reduced electric resistance and substrate flexibility [57,66,90]. However, thin silicon wafers are even more difficult to handle due to increased fragility, and their tendency to wrap and fold [38,91]. This problem was solved by the introduction of flip-bond or pick-and-place techniques, which became a key issue for handling and the assembly of ultra-thin components [38,57,66]. ...
... This problem was solved by the introduction of flip-bond or pick-and-place techniques, which became a key issue for handling and the assembly of ultra-thin components [38,57,66]. Conventionally, the fabrication of micro-chips is based on backgrinding (wafer thinning) [38,91,92] and subsequent dicing to separate the wafer into single components (compare Fig. 23). For ultra-thin wafers, in contrast, the process is reversed to prevent wafer damage caused by internal mechanical stresses and micro cracks. ...
... In the so-called "dicing by thinning" procedure (see Fig. 24), trenches are prepared on the front-side of the silicon wafer by half-cut dicing. In the following step, the wafer is grinded from the backside until the diced grooves are reached and the wafer is separated into single dies [38,91]. ...
Pressure sensitive adhesives (PSAs) are utilized for temporary applications since bonding and debonding are determined by the adhesive-substrate interface and the mechanical and rheological properties of the PSA. Moreover, a wide variety of basic materials allows for proper adjustment of the adhesive properties (tack, peel adhesion, cohesion). Where the adjustment of the adhesive’s chemical composition is not efficient enough to provide easy and clean removability in the end of the application, release functions can be incorporated into the adhesive system. The adhesive strength is reduced upon the action of external triggers such as UV-irradiation, heat, the use of electric currents or magnetic fields. Thereby, debonding may follow various mechanisms, including phase changes, chemical reactions, crosslinking and volumetric expansion. Furthermore, electrostatic attraction, polarization, shape memory effects and mechanical adhesion can be employed. This review summarizes the most important properties of PSAs and provides an overview of well-proven as well as new approaches for “debonding-on-demand” adhesive systems. In addition, the article describes proposed and already implemented applications of the presented adhesive systems in the microelectronic industry, the automotive sector and the healthcare field.
... Nowadays, as electronic applications shrink in size, thin silicon wafer is more and more crucial for advanced semiconductor technology. Stricter and higher standard are being imposed on wafer thinning technology [3]. Back grinding is still the most common wafer thinning technique and it can thin down wafers from 725 lm to less than 100 lm [4]. ...
... Although it has a high thinning speed, subsurface damage (SSD) induced by back grinding is unavoidable, including microcrack, residual stress, and dislocations [4,5]. These damages are responsible for the degraded mechanical properties of the produced wafers including low fracture strength of ultrathin silicon wafer causing handling problems and various challenges in dicing and packaging assembly [3,6]. This makes it necessary to develop damage-free postgrinding processes to realize damage layer removal and stress relief. ...
... It can be used to produce smooth silicon surface with low total thickness variation values. To get higher material removal rate, higher thrust force is required, which may induce wafer cracks and further penetration of subsurface damage [3,7]. The polishing slurry may cause environmental pollution problems and hence it is becoming a less attractive option. ...
In this study, atmospheric-pressure (AP) plasma generated using He/O2/CF4 mixture as feed gas was used to etch the single crystal silicon (100) wafer and the characteristics of the etched surface were investigated. The wafer morphology and surface elemental composition were analyzed using SEM and XPS respectively. The XPS results reveal that the Fluorine element will be deposited on the wafer surface during the etching process when oxygen was not introduced as the feed gas. By detecting the energy and intensity of emitted particles, optical emission spectroscopy (OES) is used to identify the radicals in plasma. The fluorocarbon radicals generated during CF4 plasma ionization can form carbon fluoride polymer, which is considered as one factor to suppress the etching process. The roughness was measured to be changed with the increase of the etching time. The surface appears to be rougher at first when the plasma etching occurred on the subsurface damaged layer and the subsurface cracks would show on the surface after a short time etching. After the damaged layer was fully removed, etching resulted in the formation of square-opening etching pits. During extended etching, the individual etching pits grew up and coalesced with one another, this coalescence provided an improved surface roughness. This study explains the AP plasma etching mechanism and the formation of anisotropic surface etching pits at a micro-scale level for promoting the micromachining process.
... Mechanical handling and stress cause serious problems in the packaging assembly process for ultrathin dies. A die backside 138 Page 2 of 12 metallization layer such as Cu, acting as a mechanical stabilization layer, is crucial in preventing die warpage and fractures especially during the die attach and wire bonding processes [1]. ...
... The cost of plasma dicing is very high owing to the requirement of photolithography steps to etch Si and metals in the dicing street, in addition to the slow etch rate of metals. Laser dicing is promising and it is gaining more importance in the manufacturing of thin semiconductor wafers because of its cost and quality advantages over mechanical and plasma dicing [1]. However, many effects from laser dicing on the mechanical strength and microstructure of the Si die need to be further understood, especially when dicing through Si and metal layers simultaneously. ...
Laser dicing of ultrathin dies is promising and is gaining importance because of its cost and quality advantages over mechanical and plasma dicing. However, the effects of laser dicing on the mechanical strength and microstructure of ultrathin Si dies need to be further understood, especially when dicing through Si wafers with backside Cu layer. A critical phenomenon effecting the Si die sidewall strength after nanosecond laser dicing of Si wafers with backside Cu is the formation and separation of a SiO2 layer at the sidewall. The mechanisms behind the SiO2 layer formation and separation were studied in this work. Si wafer samples without and with backside Cu layer were prepared by dicing with nanosecond laser using standard production parameters. The microstructure and phases formed were investigated by energy dispersive spectroscopy and nanobeam diffraction in a transmission electron microscope. In die samples without backside Cu, the sidewall consists of a thin surface layer of amorphous Si, followed by a polycrystalline Si layer, and finally an epitaxial Si layer. In die samples with backside Cu, the sidewall microstructure was observed to be vastly different. At the upper region of the sidewall, a surface layer of polycrystalline Cu was found, followed by a polycrystalline Cu3Si layer, a SiO2 layer mixed with Cu3Si, and finally a thick SiO2 layer. The Cu3Si catalyzes the growth of the SiO2 through an oxidation step of the Cu3Si on the sidewall surface as well as at the SiO2/Si interface. In the lower region of the sidewall, the microstructure is similar to the upper region, but there is a separation of the SiO2 layer from the crystalline Si. The SiO2 undergoes a decomposition reaction at the SiO2/Si interface, releasing volatile SiO which causes microvoids to form and grow laterally at the interface. The growth and coalescence of the microvoids eventually lead to the separation of the SiO2 layer from the crystalline Si, leaving behind a clean and rough crystalline Si surface with a peak-to-peak roughness of 100–200 nm. In the areas where the SiO2 layer has separated from the Si die sidewall, the fracture strength of the sidewall is dependent on the material property and surface roughness of the crystalline Si, and not on the SiO2 layer. In the sidewall region near the die frontside, the SiO2 thickness is more than regions near the die backside, and no microvoiding and separation at the SiO2/Si interface were detected. This is hypothesized to be due to a higher O2 pressure at the upper region of the narrow dicing trench which is open to the atmosphere compared to the lower regions where there could be O2 deprivation and lower O2 pressure.
... The main advantage here is that compared with pure oxide layers, the flexibility of HCs is greatly improved. The mechanical resistance of HCs is sufficient for the intended application proposed in this work: OLED circuits covered with HC materials can be easily diced using a standard saw dicing process, 20 can be handled and manually cleaned using soft cloth and alcoholic solvents in order to have a clean surface for further integration into a microdisplay housing optical system. HC1 and HC2 are based on same precursors, but the difference of synthesis and formulations made them significantly different in terms of structure and morphology. ...
Technical background for CMOS substrate thinning of CEA‐LETI (historically developed for through silicon via technology as well as for more recent activity to provide curved image sensors, for IR as well as for visible spectra) has been applied to realize curved OLED‐based microdisplays. It will be shown that test OLEDs made onto silicon wafers as well as 873 × 500 WVGA, 0.38″ diagonal, and an innovative 1920 × 1200 WUXGA, 1″diagonal, CMOS‐based microdisplays can be curved at R = 45 mm radius of curvature (1D) with no negative impact onto the circuit electrical characteristics. This feature can allow significant innovation on the system and application because it can help to redesign simpler and lighter optical engine systems, in the same manner as for curved image sensors. These results can be obtained owing to the integration of a new protective hard coat layer that has been used in conjunction with a robust thin‐film encapsulation to protect OLEDs from mechanical ingress (from process steps and handling) and oxidizing gas of the atmosphere, respectively. Results have been produced within the framework of the EU‐funded, H2020 project, called Large cost‐effective OLED MIcroDisplays (LOMID and their applications). A thick hard coat material replaced the rigid glass lid to protect OLED circuits The Si substrate containing the CMOS and the microdisplay was thinned down to 100 μm thick The microdisplay was curved at R = 45 mm with same functionalities as the reference microdisplay (planar)
