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The basic block diagram of an asynchronous FIFO 

The basic block diagram of an asynchronous FIFO 

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Fig. 1: An 8T 1R-1W Dual-Port SRAM cell
Fig. 2: The basic block diagram of an asynchronous FIFO 
Fig. 3: FIFO timing diagram for the scenario in which f wclkf ≤ f rclkf 
Fig. 4: Block diagram for the design with f wclkm ≤ f rclkm
+1 Fig. 5: Timing diagram for f wclkm ≤ f rclkm with T = T rclkm
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology
Conference Paper
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  • Sep 2017
With the advancement in technology nodes, the number of components operating in different clock domains in a System on Chip (SoC) increases. Asynchronous multi-port memory with dedicated write and read ports is used to allow data to cross clock domain boundaries. The dual-port memory architecture introduced in this paper, is based on the Single-Por...
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Context 1
... this write operation the EMPTY signal indicating the data availability, requires two to three read clock cycles (2 ≤ T rclkf ≤ 3) depending on the phase to change its status which is shown in figure 3 as D empty . This is caused by the two flip-flop synchronizers in the FIFO buffer shown in figure 2. The depth of the FIFO buffer for f wclkf ≤ f rclkf is to be large enough to avoid overwriting existing data before it is delivered to the read port. ...

Citations

... Se mai pot utiliza și conceptele de copii multiple ale cache-ului dar și multiporting virtual pentru a realiza o memorie multi-port cu bancuri care au 1 port. Un exemplu de realizare este referința [52]. ...
Engineering of some next generation 3D memories
Thesis
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  • Sep 2020
3D DRAM 1T1C memories and a 3D NOR memory
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