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![The PP diagram of multiplier [3] with our added parameter K for WL = 6. Blocks in gray are approximate.](profile/Mohammad-Saeed-Abrishami/publication/260737247/figure/fig1/AS:647929127788562@1531489750987/The-PP-diagram-of-multiplier-3-with-our-added-parameter-K-for-WL-6-Blocks-in-gray.png)
The PP diagram of multiplier [3] with our added parameter K for WL = 6. Blocks in gray are approximate.
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![Fig. 4. The PP diagram of multiplier [3] with our added parameter K for...](profile/Mohammad-Saeed-Abrishami/publication/260737247/figure/fig1/AS:647929127788562@1531489750987/The-PP-diagram-of-multiplier-3-with-our-added-parameter-K-for-WL-6-Blocks-in-gray_Q320.jpg)
In this paper a low power multiplier is proposed. The proposed multiplier utilizes Broken-Array Multiplier approximation method on the conventional modified Booth multiplier. This method reduces the total power consumption of multiplier up to 58% at the cost of a small decrease in output accuracy. The proposed multiplier is compared with other appr...
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... counterpart, in terms of MSE. The multiplier presented in [3] is another unsigned approximate multiplier made up from basic blocks of 2 × 2 approximate multipliers. In [3], there is no defined parameter to adjust the precision of multiplier. Hence, in our implemen- tation, we modified the design and defined the K parameter as illustrated in Fig. 4. In this method, an imaginary vertical line is introduced between the PPs, and the blocks positioned entirely on the right hand side of this line are replaced by approximate blocks and K controls the position of this line. In fact, the K parameter acts so alike to VBL in our proposed method and enhances the versatility of the design in ...
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Citations
... The primary advantage of this design lies in its compact and expedited circuitry, achieved at the expense of precision. Then, Farshchi et al. [361] modified BAM multiplier using booth encoding. Then, Roy and his colleagues realized the needs of computational applications in real-time precision demands through designing approximate and reconfigurable circuits, ensuring power consumption aligns with computational accuracy. ...
he unprecedented progress in computational technologies led to a substantial proliferation of artificial intelligence applications, notably in the era of big data and IoT devices. In the face of exponential data growth and complex computations, conventional computing encounters substantial obstacles pertaining to energy efficiency, computational speed, and area. Due to the diminishing advantages of technology scaling and increased demands from computing workloads, novel design techniques are required to increase performance and decrease power consumption. Approximate computing, nowadays considered a promising paradigm, achieves considerable improvements in overhead cost reduction (i.e., energy, area, and latency) at the expense of a modest (i.e., still acceptable) deterioration in application accuracy. Therefore, approximate computing at different levels (Data, Circuit, Architecture, and Software) has been attracted by the research and industrial communities. This paper presents a comprehensive review of the major research areas of different levels of approximate computing by exploring their underlying principles, potential benefits, and associated trade-offs. This is a burgeoning field that seeks to balance computational efficiency with acceptable accuracy. The paper highlights opportunities where these techniques can be effectively applied, such as in applications where perfect accuracy is not a strict requirement. This paper presents assessments of applying approximate computing techniques in various applications, especially machine learning algorithms (ML) and IoT. Furthermore, this review underscores the challenges encountered in implementing approximate computing techniques and highlights potential future research avenues. The anticipation is that this survey will stimulate further discourse and underscore the necessity for continued research and development to fully exploit the potential of approximate computing.
... Farshchi et al. introduce a new approximate multiplier for low-power digital signal processing that uses the Broken-Array Multiplier method to reduce power consumption by up to 58% while slightly decreasing output accuracy, as demonstrated by simulations and comparisons with accurate multipliers and other approximate designs [1]. Jiang et al. provide a review of Approximate Arithmetic Circuits, which gives a complete evaluation of several approximation strategies for improving performance and energy economy while reducing accuracy loss. ...
... F. Farshchi et al. [7] apply the above-proposed BAM to booth multiplier, a modified arrangement which helps to deal with signed binary computations. The system's power consumption was reduced by almost 50% due to the suggested approximation blocks, which also resulted in a 6dB peak reduction in the signal-to-noise ratio. ...
... In a parallel effort, novel metrics and techniques were introduced by researchers 5-7 to assess the effectiveness of approximate adder modeling. Building on these foundations, Kulkarni et al. 6 presented an approximation multiplier based on erroneous building blocks, yielding notable power savings compared to correct multipliers. ...
The main objective of this project includes, enhance the computational efficiency of
DSP systems which make them operate more efficiently. Traditional DSP computations can be slow, so sometimes it‟s more important to be fast than completely accurate. To craft a Digital Signal Processor (DSP) systems even faster and save energy, researchers have designed circuits that approximate calculations, sacrificing a bit of precision. By this proposed solution, we designed a RoBA multiplier type for filters that rounds numbers to the closest whole number. By simplifying the multiplication process, this approximation reduces system‟s size and speeds up the operation. Considering the fact that the multiplier typically functions at a slower pace compared to other components, this adjustment is anticipated to enhance the filter‟s overall efficiency. We compared the Vedic multiplier to the proposed ROBA multiplier. The acquired results showcase the power, area, number of slice LUTs, number of bonded Input/Output Buffers, and delay related to this multiplier and FIR filters were greatly decreased, while the multiplier speed increased proportionally.
... Similar to BAM, another multiplier called Broken Booth Multiplier (BBM) was also presented. 73 It applies modified Booth algorithm to generate partial products and only skip the right-hand-side adders of a vertical line. According to them, it is more efficient in terms of power than BAM. ...
... [78][79][80][81] Similar to BAM, another multiplier called Broken Booth Multiplier (BBM) was also presented. 73 It uses a modified Booth algorithm to generate partial products and only skip the right-hand-side adders of a vertical line. According to them, it is more efficient in terms of power than BAM. ...
... Broken Array Multiplier.73 ...
The limitations of scaling in CMOS technology pose challenges in meeting the requirements of future applications. To address these challenges, researchers are exploring various design techniques, including Approximate Computing (AC), which leverages the inherent error resilience of applications to achieve high performance and energy gains with desired quality. AC has gained popularity as a computer paradigm for error-resilient applications, and many researchers have studied AC across computing layers and developed tools for implementing these techniques. This paper provides a comprehensive survey of AC techniques at the abstraction levels of software and hardware and discusses the tools to implement AC in hardware and software, quality evaluation tools and comparison points. The paper also covers existing frameworks for AC, potential applications, future research directions, challenges and limitations. This information can guide researchers in identifying promising avenues for further advancements and innovations in this domain. Additionally, this paper compares state-of-the-art surveys of AC and highlights the unique features and contributions of this work that distinguish our work from previous surveys.
... For fixed-point signed approximate multiplication, Booth multipliers are widely used by adding an extra stage of Booth encoding to the conventional binary multiplier. Thus, the aforementioned architecture-level approximation techniques are applicable to Booth multipliers as well [17,56,98,100,103,104]. Given the comprehensive comparison of the above techniques in Section 7.1.1, ...
Given the stringent requirements of energy efficiency for Internet-of-Things edge devices, approximate multipliers have recently received growing attention, especially in error-resilient applications. The computation error and energy efficiency largely depend on how and where the approximation is introduced into a design. Thus, this article aims to provide a comprehensive review of the approximation techniques in multiplier designs ranging from algorithms and architectures to circuits. We have implemented representative approximate multiplier designs in each category to understand the impact of the design techniques on accuracy and efficiency. The designs can then be effectively deployed in high level applications, such as machine learning, to gain energy efficiency at the cost of slight accuracy loss.
... A low complex FIR filter based on a binary subexpression elimination method has been presented to provide neighboring channel attenuation specification and related narrow transition bands, particularly for wireless applications. The computation in FIR filter is mainly dependent on coefficient multiplication and the use of partial products in the multiplier that limits the silicon area and power requirement of the filter operation [3]. ...
FIR filter is an essential part of digital signal processing that is extensively used in many areas such as wireless applications and digital processing system. The FIR filter design is inherently stable and has a linear phase characteristic under symmetric conditions, but its implementation often involves complexity and a large filter length to achieve specific design requirements. In this paper, the complexity of the FIR filter is reduced by eliminating the repeated subexpression in a canonic signed digit (CSD) number system based filter operation. A new grouping method has been proposed for the CSD number system-based filter coefficient to minimize the number of unpaired nonzero bits in the filter coefficient. The statistical analysis of the proposed grouping method is performed and compared with other existing schemes. The number of unpaired nonzero bits in the proposed grouping scheme is reduced by an average of 24.11 as compared to other existing schemes. Further, an efficient FIR filter with hardware sharing architecture is designed and implemented to achieve a 14.65 reduction in average power consumption, and the average operation speed is increased by 10.1 compared to the other existing filter structures.
... In order to reduce the dynamic power consumption in the digital system, a retiming approach can be used. Most of the research on efficient filter design focuses on the optimization of the multiplier section of the FIR filter [1][2][3]. The efficient number system can also play an important role in the optimization of the performance of the design structure [4][5][6][7]. ...
Optimization of power, speed and hardware utilization are the major concerns in design objectives for modern digital signal processing (DSP) applications. In intermediate frequency (IF) processing unit of SDR receivers, a FIR filter is the main processing element. The redundant number system is extensively used to optimize the arithmetic operations in digital systems. This implementation can further be improved through an architectural transformation at circuit level. In this paper, the use of hybrid signed digit (HSD) number based filter coefficients is proposed for a FIR filter design. Based on the proposed HSD coefficient method in filter computation, a reduction of 16.06% in hardware resources is achieved in comparison to existing methods. In addition, a retiming architecture for an optimized FIR filter is proposed and compared with other existing approaches. The average power consumption is reduced by 13.42% and increases speed by 10.13% in comparison to other existing structures.
... To improve the performance by reducing the number of partial products and their generation complexity, various approximate Booth multiplier architectures are presented [20][21][22][23][24]. An approximate radix-4 Booth multiplier is presented in [23] that generates approximate partial products which are accumulated approximately. ...
The approximate design has emerged as a revolutionary design paradigm to obtain energy efficient digital signal processing cores while exhibiting acceptable accuracy. In different signal processing architectures, multiplier is the prime arithmetic unit and significantly influences the performance of these cores.
Therefore, four novel energy efficient rounding based approximate (RBA) multiplier architectures are proposed in this paper. These multipliers first approximate input operands to the nearest power of two values and then achieve multiplication using few adders and shifters. The proposed RBA multipliers significantly reduce implementation complexity and provide higher energy efficiency.
Further, a novel reconfigurable rounding based approximate (RRBA) multiplier is proposed to achieve desired performance-quality tradeoff. Further, the performance of proposed RBA and RRBA multipliers is evaluated and analysed over the existing approximate multiplier architectures. The proposed 8-bit RBA0 requires 59.8% (54.7%) reduced area (delay) compared to the existing approximate multiplier. Finally, the efficacy of the proposed multipliers is demonstrated in the application by implementing Gaussian filters embedded with existing and proposed approximate multipliers. The Gaussian filter designed using RBA0 provides 32.5% reduced energy consumption over the filter with existing multiplier.
... According to the work in [6] and [7], which investigated the recent studies in the area of approximate computing, the design of approximate multipliers has extensively been studied. Many approximate multipliers proposed calculate the upper bits exactly and lower bits approximately [8][9][10]. Yamamoto et al. proposed a methodology to systematically design 8-bit approximate array multipliers by gradually removing adders, and analyzed the trade-offs among circuit area, delay, power and accuracy of the approximate multipliers [11]. ...
In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.
