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Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells d...
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... be able to do exhaustive explorations in the available design space, it is important to formulate architectural models for PPA that utilize physical SRAM parameters leading to faster exploration [9]. These PPA metrics form the optimization objectives for the MSS as mapped on the axes of spider-web in fig. 1. The selection of the optimal memory becomes a cost minimization problem and a trade-off between these objectives can be performed by altering the physical parameters. In fig. 1, two MSS configurations are compared. Configuration 1 is denser and has lesser leakage while configuration 2 consumes lesser dynamic power and has a lower ...
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... utilize physical SRAM parameters leading to faster exploration [9]. These PPA metrics form the optimization objectives for the MSS as mapped on the axes of spider-web in fig. 1. The selection of the optimal memory becomes a cost minimization problem and a trade-off between these objectives can be performed by altering the physical parameters. In fig. 1, two MSS configurations are compared. Configuration 1 is denser and has lesser leakage while configuration 2 consumes lesser dynamic power and has a lower congestion. A designer chooses the configuration whose PPA best suits the requirements of the SoC. In this section we review various physical parameters that change SRAM ...
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... often a multi-objective optimization problem [10]. For example, objectives such as minimum area and low dynamic power consumption are often required at the same time. We consider that frequency of operation is a minimum imperative to be met by an MSS i.e. it acts as a hard filter. For further optimization, we have identified four axes as shown in fig. ...
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... memory compilers from a pre-characterized database. The primary function of this step is to retrieve all possible combinations of physical SRAM macros (either assemblies or singular memory instances). This step is expected to suggest many possible instance combina- tions, each of which represents a unique contour in the spider- web diagram in fig. ...
Citations
Floorplan is an important process whose quality determines the timing closure in integrated circuit (IC) physical design. And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration. Applying machine learning to the floorplan stage is a potential method to accelerate the floorplan iteration. However, there exist two challenges which are selecting proper features and achieving a satisfying model accuracy. In this paper, we propose a machine learning framework for floorplan acceleration with feature selection and model stacking to cope with the challenges, targeting to reduce time and effort in integrated circuit physical design. Specifically, the proposed framework supports predicting post-route slack of static random-access memory (SRAM) in the early floorplan stage. Firstly, we introduce a feature selection method to rank and select important features. Considering both feature importance and model accuracy, we reduce the number of features from 27 to 15 (44% reduction), which can simplify the dataset and help educate novice designers. Then, we build a stacking model by combining different kinds of models to improve accuracy. In 28 nm technology, we achieve the mean absolute error of slacks less than 23.03 ps and effectively accelerate the floorplan process by reducing evaluation time from 8 hours to less than 60 seconds. Based on our proposed framework, we can do design space exploration for thousands of locations of SRAM instances in few seconds, much more quickly than the traditional approach. In practical application, we improve the slacks of SRAMs more than 75.5 ps (177% improvement) on average than the initial design.
