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Rocket Chip Micro-Architecture

Rocket Chip Micro-Architecture

Source publication
Fig. 1: Timing histogram of (a) a baseline program, (b) after...
Fig. 3: Rocket Chip Micro-Architecture
Fig. 4: Hardware Diversification on Co-processor
Fig. 9: Comparing channel capacity of the proposed solution and the...
CIDPro: Custom Instructions for Dynamic Program Diversification
Preprint
Full-text available
  • Sep 2018
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-pr...
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Context 1
... Secured Processor shown in Figure 2 is a RISC-V architecture that includes a Rocket core, a custom defined Rocket Chip Co-Processor (RoCC), L1 caches and a Floating Point Unit (FPU) [4]. The RoCC, which executes the CIs, is a tightly integrated extension to the processor pipeline as shown in Figure 3. This enables the RoCC to stall the entire pipeline until the CI has completed its execution. ...
Context 2
... Secured Processor shown in Figure 2 is a RISC-V architecture that includes a Rocket core, a custom defined Rocket Chip Co-Processor (RoCC), L1 caches and a Floating Point Unit (FPU) [4]. The RoCC, which executes the CIs, is a tightly integrated extension to the processor pipeline as shown in Figure 3. This enables the RoCC to stall the entire pipeline until the CI has completed its execution. ...

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Fig. 1: Timing histogram of (a) a baseline program, (b) after...
Fig. 9: Comparing channel capacity of the proposed solution and the...
CIDPro: Custom Instructions for Dynamic Program Diversification
Conference Paper
Full-text available
  • Aug 2018
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-pr...
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