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![5T SRAM cell [15]](publication/346376894/figure/fig1/AS:963962208272385@1606837908739/5T-SRAM-cell-15_Q320.jpg)
![PPN based 10T SRAM [25]](publication/346376894/figure/fig2/AS:963962208268328@1606837908909/PPN-based-10T-SRAM-25_Q320.jpg)
![Low leakage 11T SRAM [31]](publication/346376894/figure/fig3/AS:963962212462592@1606837909003/Low-leakage-11T-SRAM-31_Q320.jpg)
![RD-8T SRAM cell [20]](publication/346376894/figure/fig4/AS:963962212474880@1606837909113/RD-8T-SRAM-cell-20_Q320.jpg)
![Butterfly curve to find SNM of SRAM cell [33]](publication/346376894/figure/fig5/AS:963962212450310@1606837909196/Butterfly-curve-to-find-SNM-of-SRAM-cell-33_Q320.jpg)
The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challeng...
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An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve met...
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Citations
... In static random-access memory (SRAM), the Q point, or quiescent point, represents the transistor or circuit's operating point without a signal input [11], [12]. Determining biasing conditions, such as voltages and currents, for the transistors in a 6T SRAM cell during idle states is essential in DC analysis [13]. This includes assessing the behavior of pull-up (usually PMOS) and access (typically NMOS) transistors to ensure proper SRAM functionality during read/write operations and stability during idle periods [14]- [16]. ...
... Static power dissipation occurs even when the system is in standby mode, while dynamic power dissipation is consumed during read-and-write operations in SRAM [8]. The power consumed is the product of the current and voltage drawn from the source [9]. Mobile devices require designs with low power dissipation. ...
The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.
... Numerous researchers are actively engaged in the design of memory cells tailored for space applications. However, this endeavour comes with its set of formidable challenges, primarily revolving around data integrity, area e ciency, and power e ciency [10,11,12]. Ensuring data remains accurate and reliable in the harsh space environment, characterized by radiation and temperature extremes, is a paramount concern. ...
In the satellite technology landscape, the satellite industry is crucial across military, meteorology, safety, climate monitoring, and landscape mapping sectors. The demand for high-quality satellite imagery has led to innovations in image processing and compression techniques to overcome challenges such as data storage limitations and slow upload speeds. This paper focuses on optimizing on-board SRAM memory cells for satellite image compression, addressing issues like radiation-induced errors, memory size, and power efficiency. A hybrid memory array is proposed, allocating reliable cells for Most Significant Bits (MSB) and less reliable cells for Least Significant Bits (LSB), optimizing area, power, and data integrity. The research evaluates SRAM cell sensitivity to radiation-induced Single Event Upsets (SEUs), with simulation results indicating smaller cell sizes and lower operating voltages increase susceptibility. Simulate a comparative analysis involving radiation-hardened SRAM cells, including CC18T, RHC14T, RHMC12T, SARP12T, SRRD12T, and PCELL10T, and proposed 12T. Proposed 12T cell is significantly 1.22x/3.77x/3.9x/4.1x/1.86x less write delay then CC18T/RHC14T/RHMC12T/SRRD12T/PCELL10T, respectively. Additionally, 2.27x/1.98x/71.29x lower read access time than RHMC12T/SARP12T/SRRD12T memory cells. The area occupied by our proposed cell is substantially smaller, with it being 2.03x/1.39x/1.18x/1.6x/1.09x less than CC18T/RHC14T/RHMC12T/ SRRD12T / PCELL10T. Furthermore, observed improvements in read, write and hold Noise Margins, and critical charge. Introduced an Electrical Quality Metric (EQM) to provide a comprehensive assessment of SRAM cell performance, and our proposed cell excels in terms of EQM compared to the others.
... The current challenges in SRAM designing include power consumption [3], energy efficiency [4], stability and reliability in difficult operating conditions [5], density and area for high memory density on limited chip area [6], speed and performance to meet the growing demand for higher bandwidth communication [7], process variation dealing with an increasingly complex manufacturing process [8], and security to protect against hacking and tampering [9]. To address these challenges and achieve a balance between competing design objectives, SRAMs are required that are stable, reliable, power efficient with higher speed. ...
The given work introduces a novel design of a low power 17 transistor ternary static random access memory (17T-TSRAM) cell that utilizes a 10nm gate all around carbon nanotube field effect transistor (GAA CNTFET). The proposed design aims to achieve higher speed, lower leakage power, and lower energy consumption. The design employs two 6T standard ternary inverters (STI) that are cross-coupled with differential write and single-ended read circuitry to form the proposed 17 Transistor(17T) TSRAM cell. The design is operated at a low supply voltage of 0.5 volts, which helps to minimize the overall power consumption. The accomplishment of the proposed design is evaluated by comparing it with existing designs that utilize 10nm and 32nm CNTFET verilog-A models. The results show that the proposed TSRAM design offers remarkable improvements in several key parameters like leakage power consumption, write delay, read delay, and PDP (Power-Delay Product), resulting in lower overall energy consumption. Overall, the proposed design of a low power 17T TSRAM cell using GAA CNTFET technology offers promising improvements in terms of energy efficiency and performance compared to existing designs.
... The three operating modes of the FinFET are Low Power (LP) mode, Shorted Gate (SG) mode, and Mixed LP-IG mode. The SG model is similar to a MOSFET; however, the LP model is well suited to low-power applications [7] [8]. ...
FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The outcomes of the proposed SRAM design are compared with several recent designs based on power, delay, and, and various stability analysis parameters such as read, write and hold noise margin. Finally, the article discusses the challenges in SRAM design using FinFET and provides the future direction for optimization of accuracy, area, speed, delay, and cost of the FinFET-based SRAMs.
... However, the circuit requires pre-charging of the bit-lines and does not have separate write and read ports, thus, being unable to write and read simultaneously. For reliable operations, a certain cell-ratio (CR) and pull-up ratio (PR) needs to be maintained [19]. Process variation and supply scaling make the 6T architecture inefficient in the subthreshold region [20]. ...
An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.
... Multiple circuit-level techniques to improve these parameters have been reported in recent past to address these issues. [20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39] Multiple circuit-level techniques to improve these parameters have been reported in recent past to address these issues. For addressing the issue relating to read stability, the read decoupled technique 24 has been most widely accepted due to two key advantages. ...
Radiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.
... To reduce the leakage power consumption, several schemes such as leakage feedback approach [11], stacked keeper with body bias [12] and sleepy keeper [13] have been proposed. The multi threshold voltage CMOS is also an important technique to minimize the static power dissipation [14] but data is not retained at the storage node. ...
The increasing demand of portable gadgets for emerging VLSI applications call for the low power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell has been designed using Negative Capacitance Junctionless FinFET (NC-JL FinFET) device. Further, the NC-JL FinFET based 6 T SRAM cell is evaluated for its power, stability and delay performance for read, write, and hold states and compared with conventional JL FinFET and published JL FinFET based SRAM. To investigate the reliability, the impact of ferroelectric thickness (TFE) and supply voltage (VDD) on the performance of NC-JL FinFET SRAM has also been investigated. It is shown that NC-JL FinFET SRAM dissipates 20% and ∼33% less static and dynamic power, with 1.2-, 1.5- and 1.18-times enhanced static noise margins in read, write, and hold state, respectively than JL FinFET SRAM. It also provides 37% and 20% faster read and write operations.
... The layout of the 9T SRAM cells are design based on CMOS design rule in ref. [36,37]. The area for several of 9T SRAM cell is mention in the ref. ...
... The area for several of 9T SRAM cell is mention in the ref. [36,37]. The layout is depend on the width of pull-up and pull-down transistor in the SRAM cell. ...
The growing markets for low-power electronic devices energized by battery have created the need for smaller power-efficient chips to prevent frequent charging of the source. Nowadays the market capitalization of low-power appliances is expected to grow from USD 4.9 billion by 2022 to USD 7.9 billion by 2027 as per global forecast to 2027 published by markets. The main factor leading to growth of low power electronics market includes demand of energy saving components, miniaturization, and entry of IoT (internet of things) devices. In addition, increased investment by automotive OEM (Original Equipment Manufacturer) and governments to promote the adoption of electric vehicles is expected to create more market opportunities. In this digital era, memory components play a major role in power consumption and this incites the research interest these days. CMOS (Complementary Metal Oxide Semiconductor) technology is growing rapidly towards greater integration into a single chip, resulting to a decrease in chip sizes using less space. Speed and stability demand is also growing up. Combined chip density increases as downtime technology continues. Stability and reliability are an important issue for the static random access memory (SRAM) memory device. In this paper, the design and analysis of CMOS based 9T SRAM cell in a variety of technologies is presented. The main focus of this review paper is to analyze 9T SRAM to test performance on several CMOS technologies (180nm, 90nm, 65nm, 45nm, 32nm, 14nm) with the help of a predictable technology (PTM) file. The butterfly curve method is used to examine the consistency of the SRAM bit cell in terms of static noise margin (SNM). It is clearly shown in this paper that as it progresses from 180nm to 14nm the delay decreases with stability.
... Constant impetus on augmentation of device density required for fast sensor nodes, prompts increase in capacitive load in circuit nodes, reduces current capacity, and transconductance of devices. It has become difficult for the devices of SRAM read circuits, sometimes operating in subthreshold region, to rapidly discharge capacitive bit-lines, due to aggregate of SRAM cells, within the miniscule clock period in prevailing SRAM designs [21][22][23][24][25][26]. ...
A novel read circuit for low power dual bit-line SRAM is proposed. The local sensing circuit uses differential cell current and regenerative feedback to turn into latch. This allows lower of two bit-line currents to flow into the global sensing stage which converts to suitable CMOS voltage level. The proposed local sensing circuit uses cascode amplifier and substrate bias for reduced delay of latch formation. Simulation is done using TSMC 32 nm and compared with some prevalent sensing schemes. The proposed circuit consumes average power only 30% of other prominent latch-type scheme having bit-line and data-line capacitance between100 to 200fF representing various SRAM macro structures. Leakage current of proposed circuit shows 18% improvement over the other latch-type schemes. The proposed circuit offers improved current sensitivity, improved delay by 56% compared to earlier suggested schemes and latching operation at 0.2 V supply, ensuring small memory cell size with reduced leakage with improved stability and reliability. Rigorous simulations were done for inter-die process variation, latching and overall sensing delay and clock frequency ranging from 200 MHz up to 1 GHz. The proposed scheme exhibits reduced latching and sensing delay, leakage etc. over wide temperature range and varying memory sizes. This enables its effective deployment in wireless sensor nodes.
