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![Proposed carry select adder design, where n is the input operand bit-width, and [*] represents delay (in the unit of gate delay), n = max(2n+ 2, t).](profile/Basant-Mohanty-2/publication/263050744/figure/fig3/AS:668989734793226@1536510990298/Proposed-carry-select-adder-design-where-n-is-the-input-operand-bit-width-and.png)
Proposed carry select adder design, where n is the input operand bit-width, and [*] represents delay (in the unit of gate delay), n = max(2n+ 2, t).
Source publication
In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for...
Contexts in source publication
Context 1
... proposed CSLA is based on the logic formulation given in (4) and its structure is shown in Fig.3. It consists of one HSG unit, one FSG unit, one CG unit and one CS unit. ...
Context 2
... on this, the area and delay of 2-input XOR and one full-adder (FA) is 5, 13 and 3, 6, respectively. Using these values, we have estimated delay of each intermediate and output signal of the proposed CSLA design and the estimated values are shown in the square bracket against each signal in Fig.3. The proposed n-bit CSLA involves (17n − 3) unit area and calculates the final-sum and output-carry after (n + 5) and (n + 3) unit delay, respectively, where n = max(2n + 2, t) and t is the delay associated with input-carry c in (due to previous stage carry-output delay). ...
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Citations
... In the Switch phase, the cell becomes enamored with its surroundings when it activates Coulombic cooperation with nearby cells [19]. Mohanty and Patel [20] proposed the new processes that were required to enhance the conventional carry select adder (CSLA). They examined CSLA in accordance with binary to excess-1 converter (BEC) to recognize data dependence and redundant logic operations. ...
An electrocardiogram (ECG) measures the electric signals from the heartbeat to diagnose various heart issues; nevertheless, it is susceptible to noise. ECG signal noise must be removed because it significantly affects ECG signal characteristics. In addition, speed and occupied area play a fundamental role in ECG structures. The Vedic multiplier is an essential part of signal processing and is necessary for various applications, such as ECG, clusters, and finite impulse response filter architectures. All ECGs have a Vedic multiplier circuit unit that is necessary for signal processing. The Vedic multiplier circuit always performs multiplication and accumulation steps to execute continuous and complex operations in signal processing programs. Conversely, in the Vedic multiplier framework, the circuit speed and occupied area are the main limitations. Fixing these significant defects can drastically improve the performance of this crucial circuit. The use of quantum technologies is one of the most popular solutions to overcome all previous shortcomings, such as the high occupied area and speed. In other words, a unique quantum technology like quantum dot cellular automata (QCA) can easily overcome all previous shortcomings. Thus, based on quantum technology, this paper proposes a multiplier for ECG using carry skip adder, half-adder, and XOR circuits. All suggested frameworks utilized a single-layer design without rotated cells to increase their operability in complex architectures. All designs have been proposed with a coplanar configuration in view, having an impact on the circuits’ durability and stability. All proposed architectures have been designed and validated with the tool QCADesigner 2.0.3. All designed circuits showed a simple structure with minimum quantum cells, minimum area, and minimum delay with respect to state-of-the-art structures.
... Used CSLA is to deduce the complexity of delay in carry creation and then selecting the sum [1]. The CSLA, on the other hand, greater area, and it employs multiple blocks of RCA to calculate the carry and sum by first treating the carry inputs as 0 and 1, after which the multiplexer selects the amount of sum or carry [2][3][4][5][6]. The fundamental concept of this paper is that AND/OR gates generates carry and is carried to the subsequent step, whereas only sum is chosen by the multiplexer. ...
The main areas of research in VLSI system design include area, high speed, and power-efficient data route logic systems. The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital adders. One of the quickest adders, the Carry Select Adder (CSLA), is utilized by various data processing processors to carry out quick arithmetic operations. It is evident from the CSLA's structure that there is room to cut back on both the area and the delay. This work employs a straightforward and effective gate-level adjustment (in a regular structure) that significantly lowers the CSLA's area and delay. In light of this adjustment Square-Root Carry Select Adder (SQRT CSLA) designs with bit lengths of 8, 16, 32, and 64. When compared to the standard SQRT CSLA, the suggested design significantly reduces both area and latency. Xilinx ISE tool is used for Simulation and synthesis. The performance of the recommended designs in terms of delay is estimated in this study using the standard designs. The study of the findings indicates that the suggested CSLA structure outperforms the standard SQRT CSLA.
... Advanced sensing capabilities, including biometric monitoring, are critical for enhancing the functionality of wearable security devices. Research by [12] explored non-invasive biometric sensors for continuous monitoring of physiological parameters, which can detect signs of stress or distress. Similarly, [13] demonstrated how wearable devices could utilize heart rate variability and skin conductance to assess the wearer's emotional state, providing an additional layer of safety. ...
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... A conventional carry select adder (CCSA) is an RCA-RCA configuration that picks one bit from * Author to whom any correspondence should be addressed. each pair for the final-sum and final-output-carry, and it corresponds to the anticipated input-carry (C in = 0 and 1) [2]. Carry select adder circuits are the most basic parts of all digital and arithmetic processing units [1]. ...
... Its design utilizes one OR gate, two XOR gates, and two AND gates. The existing twostage carry select adders are considered for the comparison are denoted as TSCS [2], TSCS [3], TSCS [45], TSCS [46] [2,3,7,26,[44][45][46] respectively. Conventional and XORbased adders differ primarily in that the former requires just six MOSFETs and utilizes a single 2:1 MUX instead of two XOR gates, while the latter requires a minimum of eighteen MOSFETs and substitutes two AND gates and one OR gate for two XOR gates. ...
... Its design utilizes one OR gate, two XOR gates, and two AND gates. The existing twostage carry select adders are considered for the comparison are denoted as TSCS [2], TSCS [3], TSCS [45], TSCS [46] [2,3,7,26,[44][45][46] respectively. Conventional and XORbased adders differ primarily in that the former requires just six MOSFETs and utilizes a single 2:1 MUX instead of two XOR gates, while the latter requires a minimum of eighteen MOSFETs and substitutes two AND gates and one OR gate for two XOR gates. ...
Conventional carry select adders (CCSA) have two stages and are followed by multiplexers. CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry propagation. To choose the option between an excess-1 result and a normal result, the CCSA employs a multiplexer. The proposed single-stage carry select adder (SSCSA) has a single stage and uses a new block to generate a normal and excess-1 result based on the readily available inputs (A and B). A novel architecture is developed and specifically designed to improve power dissipation and latency. It relies on a single circuit that produces normal/excess-1 results dependent on input carry. Heterogeneous logic combining CMOS, Dual Value Logic, and Transmission Gate Logic with 22 nm Fin-FETs powers the 1-bit SSCSA circuit. Better circuit regularity is displayed by the 4-bit SSCSA, as it only uses one type of 1-bit SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22 nm FinFET technology, all adders, including 4- and 8-bit adders, are designed, simulated, and examined. According to the resulting study, the 4-bit SSCSA outperforms the best adder among existing adders in terms of speed performance and power dissipation by 17.6% and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform them at every corner.
... The fundamental Ripple Carry Adder (RCA) provides simplest architecture but suffers from prolonged carry propagation delays proportional to the bit count, motivating the exploration of alternative designs [3]. Carry Skip Adders (CSA) enhance speed by preemptively calculating carry-in possibilities but introduce redundancy, also increasing area usage [4]. ...
... A sophisticated DSP system's performance is basically improved by an effective adder design. An RCA-RCA arrangement known as a conventional carry select adder (CCSA) corresponds to the expected input-carry (Cin = 0 and 1), creates a pair of sum bits and two output carry bits, and selects one from each pair for the final-sum and final-output-carry [1]. The most fundamental components of all arithmetic and digital processing units are adder circuits. ...
Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.
... [5,12] and offered a SQRT CSLA with CBL. SQRT CSLA is produced in Ref. [13] using a binary excess-1 translator and an RCA (BEC-1). Given that the size of the BEC is lower than the RCA, this design greatly lowers both power and area when contrasted with the conventional SQRT CSLA [14]. ...
... Reference [15] presents CSLA with Zero Finding Circuit (ZFC). In contrast to the pre-existing designs [13,13,16] implements the design without a MUX at the final step of the CSLA. ...
... Reference [15] presents CSLA with Zero Finding Circuit (ZFC). In contrast to the pre-existing designs [13,13,16] implements the design without a MUX at the final step of the CSLA. ...
Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits , etc. Present the most substantial area in the research of VLSI design is area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%-75% improvement in delay and 22%-56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10-15), and PDP (30.63 × 10-15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10-15), and PDP (42.9 × 10-15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay.
... The data dependency and redundant blocks can be identified in a few CaSeA designs such as [9], and redundant blocks are eliminated to improve the speed of operation. The design demonstrated in [9] exhibits less area and delay compared to [2], with the elimination of redundant blocks in CaSeA. ...
... The data dependency and redundant blocks can be identified in a few CaSeA designs such as [9], and redundant blocks are eliminated to improve the speed of operation. The design demonstrated in [9] exhibits less area and delay compared to [2], with the elimination of redundant blocks in CaSeA. The approximate addition with variable latency for unsigned and signed input operands are used to reduce the delay in a few cases and 2ʼs complement is best suitable for addition using variable latency adders [10]. ...
... The data dependency and redundant blocks can be identified in a few CaSeA designs such as [9], and redundant blocks are eliminated to improve the speed of operation. The design demonstrated in [9] exhibits less area and delay compared to [2], with the elimination of redundant blocks in CaSeA. ...
... The data dependency and redundant blocks can be identified in a few CaSeA designs such as [9], and redundant blocks are eliminated to improve the speed of operation. The design demonstrated in [9] exhibits less area and delay compared to [2], with the elimination of redundant blocks in CaSeA. The approximate addition with variable latency for unsigned and signed input operands are used to reduce the delay in a few cases and 2ʼs complement is best suitable for addition using variable latency adders [10]. ...
This paper proposes a novel architecture of novel excess-1 adder based
Carry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed
4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates such
as XOR gates are completely eliminated which exist in existing Carry Select Adders
(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cell
regularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block in
existing designs are replaced with half adders by reducing the carry propagation to
certain extent. At the outset the speed of M2CSA is improved by overcoming carry
propagation through adder blocks, especially in 32- and 64-bit adders. The area is
the major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cell
regularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. The
functional testing of all the designs is carried out using Cadence NCLaunch. All the
designs are synthesized & implemented using Cadence Genus and Innovus respectively
at 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact in
terms of area by an average of 17% compared to existing designs. The result analysis
and comparison reveal that M2CSAs are better in terms of speed and power dissipation
by 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications
... [3][4][5][6] On the contrary, biomedical signal processing systems have comparatively relaxed timing constraints but must be realized on very low-power VLSI architectures as they are packed o® into portable battery-operated modules, where power consumption and limited power density are critical issues. [7][8][9] Therefore, multiple architectures, which are even though functionally equivalent, cannot be tailored into an application before analyzing the Power-Performance-Area (PPA) cards of the architectures. Most often VLSI designers are forced to compromise between low-power consumption and high speed. ...
... For higher speed, carry-save adder is used. 8,37,38 Carry-save multiplier using Braun's scheme requires OðNÞ stages of computation. Despite this, BPM continues to pose area complexity and has high propagation delay. ...
... The multiplication algorithm, the optimization they bring in, and the mapping of the algorithms to equivalent architectures have been discussed in various literature sources. 8,15,24,39,41,42,53,55,59,61,62 The description of the digital multiplier architecture was written using VHDL and by writing suitable test-benches, their functionality (Behavioral Simulation) was veri¯ed using XSim. Next, Synthesis, RTL analysis, and Implementation were done in subsequent steps. ...
The crucial role played by digital multipliers in VLSI system design makes it indispensable to study the PPA cards of digital multiplier architectures before tailoring multiplier architecture into such systems. Therefore, in this work, we present a detailed investigation and analysis of PPA cards of popular digital multiplier architectures, for various wordlengths. Each multiplier has been implemented on Artix-7 FPGA xc7a200tfbg676-2 and analyzed using Xilinx Vivado Design Suite 2019.2. A major contribution in this paper is the study of energy profiles of the architectures, not focused on in the earlier literature. This study compares their device utilization, timing parameters, power consumption, and energy profiles. Results indicate that Dadda Tree Multiplier and Wallace Tree Multiplier (460 slices and 557 slices, respectively, for N=32 bits) are undoubtedly the least slices consuming fast multipliers, but their power consumption and energy density are high as well. For 32-bit implementation, Vedic Multiplier consumes 48.9% lower power than Dadda Tree Multiplier, while the latter occupies 30.42% lesser slices. The speed of the Vedic Multiplier is in close proximity with the tree multipliers. The energy density of Vedic Multiplier (0.3nJ/slice) is much lower than that of Dadda Tree Multiplier (0.77nJ/slice).
