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Source publication
Multi-port Static Random Access Memories (SRAM) are essential for shared data structures, especially in distributed, multi-core and multi-processing computing systems. This paper introduces an elementary multi-port memory design which can perform either dual-read or a single-write operation (2R/1W) by efficiently combining the 6 Transistor (6T) sin...
Contexts in source publication
Context 1
... proposed design, illustrated in figure 4, only utilises 6T single-port banks to realise a dual-read, single write (2R/1W) memory. It consists of two separate ports, 1 Read-Write and 1-Read only port with different sets of address (RWADDR and RADDR), control (CSN, WEN and REN) and output (Q1 and Q2) lines and a single data line (D) to write to the memory. ...
Context 2
... proposed dual-port memory design comprises of three single-port memory banks A, B and an XOR bank, each of which is half the capacity of the memory to be built. For instance, to generate a dual-port memory capacity of 1K words (W max ) of 64 bits each (shown in figure 4), the three single-port memory banks would be of the size of 512 words (W max /2) of 64 bits each. Each row of the XOR bank contains the data from both the banks A and B in XOR'ed form. ...
Citations
... Several techniques were proposed in the literature to overcome disadvantages of power and area consumptions of conventional 1R-1W DP-SRAM. Time Division Multiplexing (TDM) [8], [9] and Replica based [10] designs are among those creating extra read and write ports [11]. TDM based memory read and write operations are sequential with respect to the internal clock of the memory although it seems like a parallel execution with respect to the SoC clock, as the internal memory clock is twice the highest clock of the accessing device in the SoC. ...
With the advancement in technology nodes, the number of components operating in different clock domains in a System on Chip (SoC) increases. Asynchronous multi-port memory with dedicated write and read ports is used to allow data to cross clock domain boundaries. The dual-port memory architecture introduced in this paper, is based on the Single-Port SRAM (SP-SRAM) that can be generated in larger capacities with better performance statistics compared to the Dual-Port SRAM (DP-SRAM). The proposed design has been evaluated by comparing existing dual-port 1R-1W and 2RW designs in 28nm Ultra Thin Body and Box Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology. A memory with a capacity of 2048 words with 64 bits, shows 15%, 35%, 28% and 4.5% improvement in read power, write power, read-write power consumption and performance respectively over conventional 1R-1W DP-SRAM with equal area. The synthesis with area optimizations applied instead, shows an area advantage of 50% over conventional 1R-1W DP-SRAM, but with a degradation in performance.
