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We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CS...
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... on Cin. CSLA with BEC [4] is modified by replacing the upper RCA block with proposed parallel prefix tree while the lower RCA block with BEC circuit is retained as it is. The final sum and Cout is obtained by selecting the partial output of either proposed tree or BEC structure using MUX. The proposed CSLA structure for 16 bit has been shown in Fig. 6. Table 2 shows the experimental results of the modified CSLA compared to conventional CSLA, BEC-CSLA, BK-CSLA, LF-CSLA and KS-CSLA with respect to area, power and delay. All the simulations and synthesis are carried out using NC launch and RC compiler tool respectively. The area refers to the total area of the entire cell, power ...
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span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of node...
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... The CSLA operates in the same way as a Ripple Carry Adder (RCA); however, the RCA propagates carry signals through more full adders. This suggests that the operation moves very quickly [20][21][22]. The integration of a CSLA with reversible logic into MCML circuits involves adapting the design to the specific characteristics of MCML while leveraging the inherent power efficiency and heat minimization features of reversible logic. ...
... Although power reduction can be addressed at every design level, the maximum impact is achieved at the higher level of abstraction/ algorithmic level. The researchers mainly focus on various arithmetic algorithms to optimize the area, speed, and power of a DSP chip [6][7][8][9][10][11]. Adders are the basic building block of digital circuits. ...
... The speed of n-bit adders is based on the algorithm of the PP network, such as Kogge-stone (K_S) [16], Brent Kung (B_K) [2], and Han-Carlson (H_C) [9]. PP adders are considered to be fast adders in comparison with serial adders [10]. To optimize the speed, area and delay parameters are considered for n-bit adders: area varies linearly and the delay has an O(log 2 (n)) behavior as the size of the adder increases [25]. ...
... K_S adder shows good results in terms of speed which is further utilized in the arithmetic block for enhancing the overall performance of the circuit. Authors in [10] designed a modified PPA by considering CSlA, to enhance the performance at cost of increased complexity. ...
Approximate computing is gaining grip as a computing paradigm for computer vision, data analytics, and image/signal processing applications. In the era of real-time applications, approximate computing plays a significant role. In many computers including digital signal processors (DSP) and a microprocessor, adders are the main element for the implementation of signal processing applications and digital circuit design. The major problem for addition is the propagation delay in the carry chain. As the bit length of the input operand increases, the length of the carry chain increases. To address the carry propagation problem in digital systems, the most efficient adder architectures for VLSI implementation are classified as a parallel prefix adder (PPA) structure. In this paper, a novel methodology to implement and synthesize different adders (non-speculative and speculative) for any ASIC-based system is proposed. The proposed hybrid Han-Carlson and Kogge-stone speculative adders show improved performance (low power and delay) over the state-of-the-art approximate adders. If the approximation fails, then the proposed efficient error correction technique is activated. The proposed speculative H_C adder results in a 23.79% speed improvement over the proposed K_S adder, and 23.86% of energy is saved. The proposed architectures were synthesized for an operand bit length of 16 bits. Finally, the proposed adder is validated for an error-tolerant image processing application resulting in 41.2 dB PSNR.
... Achieving a high speed adder is a challenging task. Processors performance of a system is decided by these digital systems' speed [1]. ...
In the area of VLSI design, the focus is on reducing delays, power consumption and space, and improving speed. This paper presents the design of 32-bit modified-HSCSA using parallel prefix adder in which the basic design is based on Binary to Excess-1 Converter (BE1C) and also handouts brief review on traditional techniques used in standard BE1C, Brent-Kung (BK), Lander-Fischer (LF) and Kogge-Stone (KS). The performance of the presented 32 bit modified –CSA using parallel prefix adder is compared with traditional techniques and observed reduced delay. Verilog HDL is used to design the structure and the simulation and synthesis is carried out using Xilinx.
... As discussed earlier, in the conventional or in the standardized CSLA the performance is not good as it has a pair of n-bit parallel adders to generate sum and carry bits [4][5][6][7]. To overcome this difficulty, conventional CSLA is replaced to modified CSLA structure by using parallel prefix adders to achieve less area, power and delay. ...
A new architecture of Carry select adder has been proposed with improved switching energy using parallel prefix adder. The conventional Carry select adder is the use of two Ripple Carry Adder (RCA) and a multiplexer. The findings in this work are the replacement of one RCA block by Brent Kung adder and the other RCA block by excess-1 converter. Simulation results show that the proposed Carry select adder is proved to have improved switching energy when compared with the other adders in 45nm CMOS process. Streszczenie. Zaproponowano nową architekturę sumatora Carry Select z ulepszoną energią przełączania przy użyciu równoległego sumatora prefiksów. Konwencjonalny dodatek Carry Select wykorzystuje dwa Ripple Carry Adder (RCA) i multiplekser. Wyniki tej pracy to zastąpienie jednego bloku RCA sumatorem Brenta Kunga, a drugiego bloku RCA konwerterem nadmiaru-1. Wyniki symulacji pokazują, że proponowany sumator Carry Select ma lepszą energię przełączania w porównaniu z innymi układami w procesie 45 nm CMOS. (Techniki projektowania sumatora Carry Select wykorzystujące równoległy prefiksowy dodatek w celu poprawy energii przełączania)
The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select Adder based on a Binary to Excess-I Converter (BEC) was utilised, which required fewer logic resources than a standard CSLA and was hence more energy efficient. The fact that these CSLAs reject one sum after the calculation, however, means that they are not more efficient. As a result, the delay was not significantly decreased. It is necessary to apply the reduced logic CSLA in order to overcome this challenge. However, by employing the Gate Diffusion Input (GDI) Technique, it is possible to achieve a lower delay than the previously suggested reduced logic CSLA. The suggested technique consumes less power and has a shorter propagation latency than existing techniques. In addition, the number of transistors necessary for the circuit was reduced by implementing this GDI-based CSLA. It is possible to create an efficient adder using this technique, as seen above.
The Carry Select Adder (CSLA) is commonly used in VLSI design applications like data-processing processors, ALUs, and microprocessors to perform fast arithmetic operations. Compared to primitive designs like Ripple Carry Adder and Carry Look Ahead Adder, the regular CSLA offers optimized results in terms of area. However, it is still possible to reduce the area and power consumption of CSLA by implementing a simpler and more efficient gate-level modification. In this work, all the CSLA structures were designed using Verilog HDL while pre-layout simulation and synthesis were done using Quartus Prime, ModelSim and Synopsys EDA tools. The final results analysis obtained have proven that the BEC-based SQRT CSLA is better than regular square root CSLA (SQRT CSLA) as it has reduced total cell area by 19.54 (16-bit) and 19.44% (32-bit) as well as reduced total dynamic power by 8.52 (16-bit) and 8.75% (32-bit). Ultimately, the modified SQRT CSLA structure using BEC method showed significant lower dynamic power consumption and smaller cell area than the regular SQRT CSLA.
High-speed, efficient, and reliable processing unit at a reasonable cost is critical in microprocessor design. This analysis concentrates on enhancing the Ripple carry adder (RCA), recognized for its high-performance operation because of transistor count, power consumption, delay, and required energy. This work describes and 9-bit RCA, building from the proposed 1-bit adder and AND gate with two inputs. The proposed adder acquires an average power deduction of 30%–98%, a delay reduction of 80%–99%, and a decrement of 58%–99% power delay product (PDP) than outperforming existing adder circuits. It enables the addition of a 9-bit adder with control from the logic circuit. Experimental results indicate notable improvements in the delay of 80%–99% and 15%–54.6% of power dissipation compared to previous Adder designs for higher bits. Also, a digital control block (DCB) has designed from proposed adder designs with optimized delay and power. It enhances the function of DCB with the improvement of all circuits of DCB.
Every digital processing system may execute basic operations like adding and subtracting by using a number of binary adders with various addition durations (latency), space constraints, and power requirements. The power delaying products (PDP) of digital signal processor (DSP) components must be kept to a minimum in order to achieve greater effectiveness in extremely large-scale integration platforms. The types of adders that utilize prefixed functioning for effective additions are parallel prefix adders or carrying tree adders. Because of their capabilities for high speeds computing, parallel prefix adders are the most employed adders nowadays. It’s referred to as a carry tree adder, which is much faster than rippling carrier adders, carrier skipping adders, carrier selection adders (CSA), etc., and does arithmetic addition using the prefix function. This research compares the effectiveness of findings on the characteristics of region, latency, and power for a 32-bit implementation of several parallel prefix Ladner-Fischer adders. The Ladner-Fischer adder with a black cell requires a lot of memory to operate. To increase the effectiveness of the Ladner-Fischer adder, the gray cell can thus be used as a substitute for the black cell. The prescribed technique’s operations are divided into three primary steps: prior processing, generations, and subsequent processing. The propagation and generation phases are the pre-processing step. The generating phase concentrates on carry generation, whereas the post-processing step concentrates on the outcome. This research calculates the Logic and routing delayed effectiveness of the suggested architecture. According to the findings of the study, CSA with a parallel prefix adder performs better than the traditional adapted CSA and uses less space.
