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In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, computer graphics and cryptography. They are also a fundamental requirement in the field of quantum computation. We have investigated that the purposes of designing reversible logic are to decrease the number of reversible gates, garbage...
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... 1: There can be any number of dimensions for a reversible gate, but lower dimension is always preferable for designing efficient circuits. The popular reversible gates are Feynman Gate (FG) [7], Toffoli Gate (TG) [8], Peres Gate (PG) [9], Fredkin Gate (FRG) [10], Feynman Double Gate (F2G) [11] and New Fault Tolerant (NFT) [12] which are shown in Fig. 2. ...
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In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease...
Traditional logic circuit emits energy into the environment due to information loss, and it is referred to be irreversible logic circuits. Reversible logic circuit is capable of diminishing power loss, quantum cost, and garbage output. Many academics have recently embraced reversible logic-based circuits exploiting all-optical technology to conduct...
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Citations
... There are a number of reversible logic gates that exist in present literature as given in [36,100,103,104,105]. In this study, we attempt to present all the reversible gates that are not covered by previous review papers which may be helpful to researchers. ...
The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum Cost, Complexity, and other performance evaluation measures. The analysis of several reversible gates is presented in this paper and provides a comprehensive overview of reversible gates, encompassing their fundamental principles, design methodologies, and diverse applications. Reversible logic circuits allow for the production of both unique outputs and distinct input combinations. The majority of the findings about the reversible gates from previous research papers are discussed and contrasted. All the reversible gates that have been proposed till now are presented in tabular form and the parameters are discussed to help the researchers to find every detail related to the reversible gates. To highlight our understanding, we have ended most of the sections with questions. The inclusion of questions is likely intended to stimulate further discussion and promote a deeper understanding of the material presented in this paper. These questions can serve as prompts for readers to reflect on the content and potentially explore related research directions or areas of improvement.
... TRLIC is calculated based on Eq. (1), TRLIC has been represented as total reversible logic implementation cost where NG is several gates, GO Garbage Outputs; CI represents Constant inputs, Gate QC represents Quantum cost [20,21]. Performance analysis of 3 methods has been analyzed with TRLIC parameter of Garbage outputs, Constant inputs (CI), Gate counts (GC), and Quantum cost (QC). ...
In terms of technological advancement, digital circuit design plays a vital role. Every application needs efficient designs for high-speed and low-power consumption devices. The need for resource constraint devices is overgrowing because of the increased adaptation of IoT and Wireless Sensor Networks for home and industrial automation. For any digital components for such devices, multiplier modules are essential in the digital circuit design. Effective multiplier designs have achieved the digital components' speed, delay, and power efficiency. The Vedic multiplier is considered the most efficient among the various multipliers due to its ability to process inputs in parallel. Another major challenge in digital circuit design is reducing power consumption and avoiding information loss. In terms of irreversible logic, heat is wasted during computing due to information destruction, which is not concerned with processing. To overcome this situation, reversible logic has been introduced with reversible gates. Thereby, this work aims to explore the possibility of developing reversible Vedic multipliers with reduced delay and higher power efficiency with improved design and implementation aspects. In this work, three models with Vedic Multiplier designs using different reversible logic circuits with low power, speed, and area-efficient reversible logic are proposed to address the lower hardware complexity resulting in a better speed of operations and reduction of power dissipation. The low number of adders in the Vedic multiplier diminishes area and power dissipation and increases the operational speed. The proposed reversible logic methods achieved low power consumption with zero information loss and increased delay.
... NFT gate [18]: P = A ⊕ B, Q = BC ⊕ AC , R = BC ⊕ AC. 11. TS-3 gate [19]: P = A, Q = B and R = A⊕B⊕C. 12. TS-3 gate [19]: P = A⊕ B, Q = B⊕ C and R = C. 13. ...
... TS-3 gate [19]: P = A, Q = B and R = A⊕B⊕C. 12. TS-3 gate [19]: P = A⊕ B, Q = B⊕ C and R = C. 13. SAM gate [20]: P = A,Q = AB ⊕ AC, Q = AC ⊕ AB . ...
Quantum computing is a modern technology that uses the laws of quantum mechanics to tackle issues like irreversibility and power dissipation, which are beyond the scope of traditional computing paradigms. To exploit quantum physics in many application fields, circuit design using reversible gates is a crucial task. In this paper, quantum implementation of three-input/three-output (3 × 3) reversible gates is presented. The functional matrices of most of the gates are presented for the first time in this paper. In addition, the quantum implementation of URG, FRSG1, R and JTF1 gates, which find importance in various practical applications, is presented for the first time in this paper. The paper concludes with a comparison of the performance parameters of reversible gates for efficient quantum circuit realization. It is shown that each gate has additional advantages in valid perspectives. The paper thus provides a useful library of 3 × 3 reversible gates for the implementation of higher-order quantum circuit design.
... A reversible gate can be represented by a reversible function with n-bit data for both input and output, where n-bit data are a sequence of bits x 1 , x 2 , . . . , x n of length n in which the mapping is bijective function on the set (0, 1) n of n-bit data on itself [16]. ...
Several works have been conducted regarding the reduction of the energy consumption in electrical circuits. Reversible circuit synthesis is considered to be one of the major efforts at reducing the amount of power consumption. The field of reversible circuit synthesis uses a large number of proposed algorithms to minimize the overall cost of circuits synthesis (represented in the line number and quantum cost), with minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter which needs to be tackled, especially for large-scale circuits which need to be realized by cascades of reversible gates. Reducing the synthesis cost can be achieved by Binary Decision Diagrams (BDDs), which are considered to be a step forward in this field. Nevertheless, the mapping of each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we implement the idea of the subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuit synthesis time. Considering Depth-First Search (DFS), we convert an entire BDD subtree in one step into a cascade of reversible gates. A look-up table for all possible combinations of subtrees and their corresponding reversible gates has been constructed, in which a hash key is used to directly access subtrees during the mapping process. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95% on average), preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.
... The reversible gates have been used to obtain different reversible functions. [10][11][12][13] The efficiency of the gates has been compared based on the number of gates used, quantum cost, garbage etc. The constant inputs added to make the gate reversible or to obtain some function were considered as extra burden in reversible circuits. ...
Stochastic computing is reemerging as one of the alternative technique of conventional binary computing for error tolerant, low‐power, and low resource applications. In the recent past, several works have been reported for the implementation of stochastic circuits. All these works have been carried out using irreversible gates or Boolean functions as building blocks, which will not be supported in the near future for the power efficient realizations due to Landauer principle. Therefore, it is timely to consider the reversible stochastic computing design. Till date, as per the author's best knowledge, no work has been reported on the reversible stochastic computing. Besides, no work has been reported on the study of feasibility of existing reversible gates for stochastic computing. In this paper, reversible gates have been examined for their stochastic operations in unipolar, bipolar, and inverse bipolar formats. In addition, some novel universal reversible gates are proposed, which are well suited for reversible stochastic computing using these formats. Finally, the implementation of reversible two‐input linear neuron using the proposed reversible gates has been demonstrated.
... 18. 3*3 TS-3 gate [22,23]: ...
Stochastic computing is a promising technique for addressing the problems of increase in leakage current, increased sensitivity to soft errors etc. in today's semiconductor industry. Stochastic computing has been presented in open literature in detail. However, power dissipation due to bit loss has been neglected in stochastic computing which can be addressed by considering reversible circuits. Consequently, there is a need to design reversible stochastic computing systems. Therefore, the paper describes the reversible stochastic circuits and the stochastic functions implemented by already existing reversible gates (up to 3*3) in Ratioed, Unsigned Extended and Signed Extended Stochastic Logic Formats. Some novel reversible stochastic gates performing various operations in these formats are proposed, which as per the author's best knowledge, are the only reversible gates, which can perform some arithmetic operation in these formats. Finally, the implementation of reversible two-input linear neuron using the proposed reversible gates has been demonstrated.
This book presents high-quality, peer-reviewed papers from the Third International Conference on Advanced Computational and Communication Paradigms (ICACCP 2021), organized by Department of Computer Science and Engineering (CSE), Sikkim Manipal Institute of Technology (SMIT), Sikkim, India during 22 – 24 March 2021. ICACCP 2021 covers an advanced computational paradigms and communications technique which provides failsafe and robust solutions to the emerging problems faced by mankind. Technologists, scientists, industry professionals and research scholars from regional, national and international levels are invited to present their original unpublished work in this conference.
