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![Measurement setup of the system-level ESD test with the indirect contact-discharge test mode, as specified in the IEC 61000-4-2 standard [2].](publication/350148913/figure/fig2/AS:1002745360297986@1616084532529/Measurement-setup-of-the-system-level-ESD-test-with-the-indirect-contact-discharge-test.png)
Measurement setup of the system-level ESD test with the indirect contact-discharge test mode, as specified in the IEC 61000-4-2 standard [2].
Source publication
Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immu...
Contexts in source publication
Context 1
... will be tested. These three TVSs are all declared that it can be used as 3.3-V I/O port protection device. The EUT without TVS also will be tested as a reference. With the system-level ESD immunity test to these EUTs, we can investigate the impact of different holding voltages of TVS to the input or output ports of the microelectronics system. Fig. 4 shows the measurement setup of the system-level ESD immunity test with the indirect contact-discharge test mode, as specified in the IEC 61000-4-2 standard [2]. The EUT in Fig. 4 is the whole PCB with power supplies (3.3 V) shown in Fig. 3. The system-level ESD gun with specified ESD voltage is zapping to the horizontal coupling plane ...
Context 2
... ESD immunity test to these EUTs, we can investigate the impact of different holding voltages of TVS to the input or output ports of the microelectronics system. Fig. 4 shows the measurement setup of the system-level ESD immunity test with the indirect contact-discharge test mode, as specified in the IEC 61000-4-2 standard [2]. The EUT in Fig. 4 is the whole PCB with power supplies (3.3 V) shown in Fig. 3. The system-level ESD gun with specified ESD voltage is zapping to the horizontal coupling plane (HCP), and the ESD energy will be coupled to the EUT [11]. The tested ESD level will start from 1000 V, and the increased step of ESD level is 1000 ...
Context 3
... the system-level ESD immunity test (as illustrated in Fig. 4), the measured voltage waveforms at the output pin of IC-1 and the output pin of IC-2 with TVS-1 protection during the system-level ESD test of +1000 V zapping are shown in Fig. 5. Before the ESD zapping, the initial states Measurement setup of the system-level ESD test with the indirect contact-discharge test mode, as specified in the ...
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Citations
... ESD protection can be divided into off-chip and on-chip ESD protection according to different protection positions. Off-chip ESD protection devices are mainly Ceramic Capacitors, Zener Diodes, Schottky Diodes, Multi-Layer Varistor (MLV) and Transient Voltage Suppressors (TVSs) [4][5][6][7][8], which are generally placed in the peripheral circuits of the chip. However, off-chip ESD protection devices are difficult to integrate and cannot meet the miniaturization requirements. ...
On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO2 dielectric for ESD protection was proposed, and the physical mechanism of its operation was investigated in detail. Experimental evaluations, utilizing transmission line pulse (TLP) testing and fusing performance analyses, reveal that the E-fuse, constructed with a Ni metal layer measuring 5 μm in width, 100 μm in length, and 5 nm in thickness, achieved a significant ESD protection voltage of 251 V (VHBM) and demonstrates low-voltage fusing at a bias voltage of 7 V. Compared to traditional ESD protection devices, the E-fuse boasts a smaller size and removability. To assess fusing performance, devices of varying sizes were tested using a fusing lifetime model. This study supports both theoretical and empirical evidence, enabling the adoption of cost-effective, straightforward E-fuse devices for ESD protection.
... The assessment of the operational efficiency of the Safety Transient Voltage Suppressors (STVS) covers two aspects: Failure Modes and Effects Analysis (FMEA) and testing the operation of the Transient Voltage Suppressors (TVS) circuit using a 1 kV transient voltage with waveform duration of 184/380 μS, as shown in Fig. 5, to determine the clamping voltage of the circuit [15][16][17][18][19], as shown in Fig. 12. ...
This research presented the utilization of Safety Transient Voltage Suppressors (STVS) in the track circuits of railway signaling systems, occurring during circuit switching due to changes in track occupancy conditions, resulting in damage and malfunction of the BR966F2 relay. The study employed Failure Modes and Effect Analysis (FMEA) combined with 1kV actual transient overvoltage testing featuring a waveform slope of 184/380 μs. Results revealed two transient voltage suppression levels encompassing Set A_(a,b), Set B_(a) and Set C_(a,b) as well as Set A//Set B//Set C and All Mode. These configurations achieved a clamping voltage of 41.6 V, categorized as Stage 1. Configurations like Set A_(c), Set B_(b,c) and Set C_(c) displayed increased series circuit behavior leading to a clamping voltage of 48.6 V, categorized as Stage 2. The application of STVS device in the track circuit of the signaling system reduced the transient voltage by diversion of the Transient Current or ISTVS through the STVS device into the ground system or the clamping voltage at the STVS device. This prevented the transient power from flowing into and damaging the relays of the track circuit, leaving only the clamping voltage with a missing peak wave. This contributed to the stability of the track circuit within the railway signaling system while also raising the Safety Integrity Level (SIL) to a higher standard, in accordance with the specifications of IEC 16508-4 and the unique requirements of the State Railway of Thailand. These enhancements increased the advanced safety system within the track circuit, particularly for train control and train operation functions of the State Railway of Thailand
... When it is exceeded, electrostatic discharge (ESD) most likely happens to cause direct breakdown or invisible inner damage [1]. Although ESD protection technologies have been taken into consideration in the circuit designs [2][3][4], in the preliminary stages of manufacturing, the fundamental elements are still under risks of ESD failure. For instance, in the organic light-emitting diode (OLED) screen factories, static charge might arise to 5000 volts on glasses, after such manufacturing processes as surface cleaning, physical vapor deposition, and photoetching [5][6][7]. ...
Electrostatic voltage is a vital parameter in industrial production lines, for reducing electrostatic discharge harms and improving yields. Due to such drawbacks as package shielding and low resolution, previously reported electric field microsensors are still not applicable for industrial static monitoring uses. In this paper, we introduce a newly designed microsensor package structure, which enhances the field strength inside the package cavity remarkably. This magnification effect was studied and optimized by both theoretical calculation and ANSYS simulation. By means of the digital synthesizer and digital coherent demodulation method, the compact signal processing circuit for the packaged microsensor was also developed. The meter prototype was calibrated above a charged metal plate, and the electric field resolution was 5 V/m, while the measuring error was less than 3 V, from −1 kV to 1 kV in a 2 cm distance. The meter was also installed into a production line and showed good consistency with, and better resolution than, a traditional vibratory capacitance sensor.
A useful design methodology to implement the bi-directional electrostatic discharge (ESD) protection circuit with uni-directional ESD device was proposed. The proposed design methodology leverages the uni-directional ESD devices and diodes, those already verified and supported by the foundry, to build the bi-directional ESD protection circuit for the desired I/O applications. The circuit exhibits several advantages, including simplified design, reduced size, and compatibility with differential or multiinput signal applications. The experimental results have validated the effectiveness and usability of the proposed circuit in providing bi-directional ESD protection. This work contributes to the advancement of ESD protection design, offering a practical and efficient solution to meet the requirement of bi-directional ESD protection.
The reliable operation of an integrated circuit (IC) can be affected by transient electromagnetic disturbances and temperature variations. In this paper, the performance of three oscillator circuits, namely 3- and 5-stage current-starved voltage controlled oscillators and a 3-stage ring oscillator, is compared with respect to electrical fast transients (EFT) under the influence of thermal stress. The main objective is to compare and assess, by means of measurements, the EFT immunities of integrated oscillators with the same electrostatic discharge (ESD) protections but different circuit topologies. The failure modes caused by EFT are proposed based on the considered failure criterion. Moreover, the importance of the IC package on the immunity levels of each oscillator is investigated. The output frequency response of each oscillator to the combined EFT and temperature stresses is analyzed without the external parasitics. The results show that the 5-stage CSVCO is most resilient towards temperature variations, whereas it is the least immune to the combined effect of EFT and temperature. Moreover, a distinct behavior in each tested oscillator’s frequency is observed for the in-phase EFT injections due to the topology of the circuit. Relevant MOSFET characteristics such as on-state drain-to-source resistance, power dissipation, effective mobility and threshold voltage are further analyzed under the influence of thermal stress and EFT. The root cause of higher EFT susceptibility of the 5-stage CSVCO is found to be the considerable variation of the on-state resistance due to the combined reduction of effective mobility and absolute threshold voltage levels of the MOSFETs.
The I/O of CMOS integrated circuits of for FlexRay communication has to be tolerant with the input signals of ±60 V in its normal applications. Thus, the on-chip electrostatic discharge (ESD) protection devices for such I/O pin must be kept off unless the bus voltage is higher than 60 V or lower than −60 V. In this work, the bi-directional p-n-p (Bi-PNP) device was proposed and optimized for bi-directional ESD protection in the FlexRay communication systems. The proposed Bi-PNP devices were verified in a 0.15-
BCD technology. The relationships between the layout spacing of doping layers and other device characteristics, including trigger voltage (Vt1) and breakdown voltage (BV), were investigated, respectively. The size dependence on the ESD robustness was also studied. The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated. Finally, the recommended size and parameters of the proposed Bi-PNP device for ±60 V FlexRay application are provided.
