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Layout of staircase, channel hole and contact holes
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3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, howev...
Context in source publication
Context 1
... loading effect during the photoresist trimming process. Therefore, in order to reduce the measurement error, the SS0 patterns and the distance measurement points of SS to SS0 should be far away from the rounding edges. However, there are still rooms for SS0 to be placed at the redundant area in a chip where there are no contact holes as shown in Fig. (10), while the reference mark needs to cross places with contact holes. ...
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Variations in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. The electric field difference in the circular and spike regions causes nonuniform trapped electron density in the charge trap layer (CTL) and influences the VTH variation. Such less-trapped electron (LT)...
Citations
... Fortunately, several types of the two-directional-staircase-forming method have been developed, where staircases are made not only in the direction along a WLy but also in the direction perpendicular to the WL. [97,98] By using this method, both the lithography cost and WLy contact area could be remarkably reduced. ...
Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ∼15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176 layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate versus charge‐trap‐layer), array‐level circuit architecture (NOR versus NAND), physical integration structure (two‐dimensional versus three‐dimensional), and cell‐level programming technique (single versus multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices. This article is protected by copyright. All rights reserved
Thin material layers are common structures in modern semiconductor device fabrication and are particularly necessary for light-emitting diodes and three-dimensional NAND memory devices. Such layers are not only deposited on the flat wafer surface but are also partially removed during subsequent etching steps. Level-set based process TCAD simulations are capable of representing flat thin material layers, such as those occurring after deposition, with sub-grid accuracy. However, topographical changes during etching processes modeled via Boolean operations expose the low underlying grid resolution, leading to detrimental artifacts. We present a novel algorithm that analyzes the thickness of all material layers and derives a refined target resolution for local regions of thin layers affected by the etching process. This allows to accurately represent topographical changes in thin layers by hierarchically refining the grid without unnecessary refinement in unaffected regions of the domain. We simulate the fabrication of a light-emitting diode device using our algorithm to automatically predict the optimal resolution for all etched material layers. Our algorithm selects efficient refinement factors to obtain the local target resolutions of the hierarchical grids, and achieves a three times faster computation time than a benchmark refinement algorithm based on topographical features.
