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We have simulated the phase noise of a voltage controlled
oscillator (VCO) using an RF circuit simulator, SpectreRF<sup>TM</sup>.
This simulator uses a variation of the periodic noise analysis first
proposed by Okumura, et al (1993). It computes the power spectral
density of the noise as a function of frequency. By assuming that only
white noise so...
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Context 1
... Simulation Frequency [Hz] Next, we measured the VCO jitter directly on a dig- ital oscilloscope. The jitter in the length of N adjacent cycles at 70 MHz is plotted on Fig. 4. The 3 curves in Fig.4 show the measured and sim- ulated jitter (AHDL-level simulation) in the length of N cycles and the line from the measured jitter ex- trapolated from the region where the icker noise is considered small. We can calculate the jitter for one cycle from the extrapolated line in Fig.4 indicates that the error of ...
Context 2
... Simulation Frequency [Hz] Next, we measured the VCO jitter directly on a dig- ital oscilloscope. The jitter in the length of N adjacent cycles at 70 MHz is plotted on Fig. 4. The 3 curves in Fig.4 show the measured and sim- ulated jitter (AHDL-level simulation) in the length of N cycles and the line from the measured jitter ex- trapolated from the region where the icker noise is considered small. ...
Context 3
... jitter in the length of N adjacent cycles at 70 MHz is plotted on Fig. 4. The 3 curves in Fig.4 show the measured and sim- ulated jitter (AHDL-level simulation) in the length of N cycles and the line from the measured jitter ex- trapolated from the region where the icker noise is considered small. We can calculate the jitter for one cycle from the extrapolated line in Fig.4 indicates that the error of simulated jitter is less than or equal to 2 dB which is satisfactory for practical use. ...
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... Since, in most practical cases, the PLL includes more than one hundred transistors, and the output spectrum should be computed over at least seven decades of frequency (e.g., from 1 kHz to 10 GHz), the simulation time may easily exceed several days or even weeks per trial. This issue is typically overcome relying on behavioral models [4]- [9], which have been built to solve some of the limitations of continuous-or discrete-time LTI models. In fact, it is known that LTI models describe just the average behavior of the PLL and therefore they do not capture the spurious tones internally generated by the PLL (e.g., reference spurs) [10]. ...
... v n being the n-th output coefficient of the PXF and φ n its phase. Once the ISF is known and (32) is used to derive the excess phase induced by the disturbance, the divider model in (9) can be modified by adding a new term, ...
The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to the prohibitive time needed to derive output noise, spurs, and transient performance from detailed transistor-level simulations. To overcome this limitation, behavioral models are needed but they must be accurate and time-efficient. This paper introduces a new behavioral macro-model of the charge-pump PLL, addressing both spectral analysis and lock-in transient computation. To meet both accuracy and simulation efficiency, the model accounts for the time-variant transfer of noise and disturbances, and a novel procedure is introduced to extract the model parameters via transistor-level periodic steady-state simulations. To describe the nonlinear dynamics, the model also includes the voltage-controlled oscillator and charge-pump nonlinear characteristic computed via transistor-level simulations. The proposed macro-model has been tested on a 2.765-GHz PLL, and the results are compared against the noise transient simulation of the PLL full netlist. Phase noise and amplitude of spurious tones, both inherently generated and induced by external disturbances, are predicted within ±2 dB. Lock-in transients are also described with an accuracy within a few percent. On the other hand, the simulation time reduction is two/three orders of magnitude for both spectral analyses and transient simulations, depending on the PLL parameters.
... For that reason, we use a especial function of Verilog-A idtmod() . This function combines an integrator and a modulus operation which is used to make an efficient of the VCO without numerical problems [9]. Therefore, the VCO can also be described using the VCO relationship (G V CO ) for the output phase deviations and the control voltage: ...
... In addition, the FFS's error and noise sources can be concentrated in these subsystems [2]. Note also in Fig. 1 the command transition, which incorporates the non ideal performances as time jitter for the FFS [8], [9]. In spite of the simplicity and acceptable correspondence with experimental results, the models describe phase noise in FFS for a limit of frequencies offset from the carrier because the command transition imposes some constraints at the simulation time. ...
... There are analytical expressions which allow to express the quantity of displacement from the expected values in each domain. These mapping functions are widely accepted in the literature and have shown a good matching to the physical FFS perdormance [7], [8]. Typically, behavioral models for VCOs and Frequency synthesizers are described with long term and short term jitter of the output signal. ...
... The error can be represented as a time function ( j (t)) having a normal distribution. Starting from a jitter free signal; the error can be added as in [8], [9]: ...
This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.
... 1. In one common phase noise generation method presented in [105,106], the step-specific perturbed frequency f VCO + ∆f VCO is integrated from t =0 up to t, which causes a discontinuous phase change whenever ∆f VCO is updated. In this case, the comparatively large and discontinuous phase changes lead to significant signal discontinuities. ...
... Shooting methods are applicable even for circuits that react in a strongly nonlinear fashion to large stimuli applied to the circuit, such as the clock or a local oscillator (Takahashi, Ogawa, & Kundert, 2002). This approach requires a few iterations. ...
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... In this table, the Frequency represents the average experimental frequency that is obtained by measuring six oscillators fabricated in six different chips. The Phase Noise metric has been obtained indirectly from experimental results ( Figure 19) using the procedure shown in [30]. The Output voltage and Power denotes the amplitude of the generated signal and power consumption (this value does not include the power of the dividers, buffers, pads, etc.) of the ring oscillator, respectively. ...
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A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex
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PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator
(VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code
controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved
by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent
Channel Power Ratio (ACPR) are −19.9 and −20.7dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built
here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed.
The testing results show that the reference spurs are −61.2dBc@20MHz and −57.7 dBc@40MHz at the output of the PLL, and
−70.5dBc@20MHz and −66.6 dBc@40MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency
divider has a phase-noise contribution of only 0.5dBc/Hz@500kHz and 0.2dBc/Hz@1MHz.
KeywordsTransceivers–Phase-Locked Loops–Frequency synthesizers–Modulators–Divider circuits–Spurs–Phase noise
... 1) The phase frequency detector, charge pump, and frequency divider are replaced with standard behavioral models, using ideas from [102]. These will not be synthesized. ...
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The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs ear-
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ly in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows
... Simulation tools are extensively used in design processes for finding a good balance between design metrics to meet the performance requirements. Unfortunately, existing full circuit simulation tools (such as SPICE [2]), are very inefficient for the simulation of PLLs at the transistor level [3]; and this problem worsens when dealing with frequency synthesizers with large divide ratios. It is not uncommon for many months to be required to finalize the design of today's advanced PLLs. ...
We present a novel method for generating small, accurate PLL macromodels that capture transient response and jitter performance with unprecedented accuracy, while offering large speedups. The method extracts and uses a highly accurate oscillator phase macromodel termed the TP-PPV macromodel. The core idea behind the novel extraction procedure is to combine concepts from strongly nonlinear trajectory piecewise macromodeling techniques together with PPV-based time shifted nonlinear phase macromodels. As a result, TP-PPV generated macromodels offer excellent global as well as local fidelity. These properties are necessary for handing large excursions in PLL control voltages during capture/lock in, e.g., hopping frequency synthesizers. We validate TP-PPV on a 5-stage interpolative ring VCO based PLL and compare results against full simulation, as well as against prior macromodels. We show that, unlike prior macromodels that only work well when the control voltage of the VCO has small excursions, the TP-PPV macromodel provides near-perfect matches against full SPICE level simulation over a wide range of design scenarios, while achieving speedups of about three orders of magnitude
