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HW/SW verification flow on FPGA platform

HW/SW verification flow on FPGA platform

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Conference Paper
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This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodolog...

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Context 1
... the described methodology would extend the core idea into an implemented analyzing tool in Section III. Figure 4 shows the verification flow on FPGA emulation (by using Versatile baseboard [12]) with implemented SoC environment. Our 3DG SoC platform execution follows the OpenGL ES 1.x for fixed function hardware, so the SW mod- ule(usually called API) will execute first and then transfer ex- ecuted data (context table, object data) into the next execution step -HW module. ...
Context 2
... using the analyzing tool, SW module will be verified first than HW because of the executed order of SoC. Figure 4(a) shows the flow of SW simulation and SW's verification. The SW simulation's results which executed by processor (ARM926EJ-S) of FPGA platform will be recorded as output frame files by analyzing tool. ...
Context 3
... proposed tool in Figure 5 will assist designers to compare SW output results and golden patterns results, and then guarantee to verify the SW module only out of HW dependent design. As the circular verifying flow of Figure 4(a) to Figure 4(b), it will detect unobvious er- rors and correct the SW problems independently before HW executing. The more detailed will be discussed in Section III. ...
Context 4
... proposed tool in Figure 5 will assist designers to compare SW output results and golden patterns results, and then guarantee to verify the SW module only out of HW dependent design. As the circular verifying flow of Figure 4(a) to Figure 4(b), it will detect unobvious er- rors and correct the SW problems independently before HW executing. The more detailed will be discussed in Section III. ...

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Citations

... Each test bench has four modes, namely the GE mode, RE mode, single frame mode, and multi-frame mode. The other type of test benches cooperates with OpenGL ES 1.x [28] and owns multiple objects per frame, as shown inTable 7 of Section5. ...
... The framebuffer viewer is used to output the file, as shown inFigure 9. The diff command can also be used to compare the data to the expected log data [28]. ...
... The latency and stability of the Internet cause the deviation of simulation time. Our lab have already developed the OpenGL ES 1.x working with our 3D graphics SoC on Versatile PB [28] . The authors migrated these 3D graphics test benches from Versatile PB to our proposed Internet-based platform and adjusted the QEMU interface and the SCI to comply with the data flow of these test benches. ...
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... The PCM [4] collects real-time statistics of a 3DG application running in hardware, including the vertex rates, pixel rates, tile num- bers, memory access, bus idle/busy counts, and data transfer rates and conflict/busy/wait information of each bus master etc. The re- lated information of 3D graphics hardware execution can be provided by monitoring tool as summarized in Table I. ...
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