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This paper proposes an efficient HW/SW integrated verification methodology for 3D Graphics (3DG) acceleration on SoC development. The proposed methodology is built for verifying 3DG SoC with FPGA emulation and contains a GUI analyzing tool for displaying emulation results and assisting HW/SW debugging automatically. With the verification methodolog...
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... the described methodology would extend the core idea into an implemented analyzing tool in Section III. Figure 4 shows the verification flow on FPGA emulation (by using Versatile baseboard [12]) with implemented SoC environment. Our 3DG SoC platform execution follows the OpenGL ES 1.x for fixed function hardware, so the SW mod- ule(usually called API) will execute first and then transfer ex- ecuted data (context table, object data) into the next execution step -HW module. ...
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... using the analyzing tool, SW module will be verified first than HW because of the executed order of SoC. Figure 4(a) shows the flow of SW simulation and SW's verification. The SW simulation's results which executed by processor (ARM926EJ-S) of FPGA platform will be recorded as output frame files by analyzing tool. ...
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... proposed tool in Figure 5 will assist designers to compare SW output results and golden patterns results, and then guarantee to verify the SW module only out of HW dependent design. As the circular verifying flow of Figure 4(a) to Figure 4(b), it will detect unobvious er- rors and correct the SW problems independently before HW executing. The more detailed will be discussed in Section III. ...
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... proposed tool in Figure 5 will assist designers to compare SW output results and golden patterns results, and then guarantee to verify the SW module only out of HW dependent design. As the circular verifying flow of Figure 4(a) to Figure 4(b), it will detect unobvious er- rors and correct the SW problems independently before HW executing. The more detailed will be discussed in Section III. ...
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Citations
... Each test bench has four modes, namely the GE mode, RE mode, single frame mode, and multi-frame mode. The other type of test benches cooperates with OpenGL ES 1.x [28] and owns multiple objects per frame, as shown inTable 7 of Section5. ...
... The framebuffer viewer is used to output the file, as shown inFigure 9. The diff command can also be used to compare the data to the expected log data [28]. ...
... The latency and stability of the Internet cause the deviation of simulation time. Our lab have already developed the OpenGL ES 1.x working with our 3D graphics SoC on Versatile PB [28] . The authors migrated these 3D graphics test benches from Versatile PB to our proposed Internet-based platform and adjusted the QEMU interface and the SCI to comply with the data flow of these test benches. ...
Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this paper, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.
... . Block diagram of 3D graphics SoC [1]. Three dimension (3D) graphics applications have gained significant popularity in the recent decades. ...
As today's consumer electronics get increasingly portable and ubiquitous, rising complexity succeeds to more functionalities integrated. Market dynamics and competitiveness further squeeze the time-to-market requirement, consequently pushing system designers to the very throughout consideration during the development process. Traditional development approaches could not satisfy with such compact demands. This paper presents a novel virtual machine (VM)-based SoC design method for developing the 3D graphics applications which makes different designers work together simultaneously and guarantees the consistency of the test benches among software and several abstraction levels of hardware to expedite the overall development process. The proposed general VM-based platform suits for HW/SW co-design. To reduce simulation time, the authors enhance the general interface as application-specific interface without modification of developing hardware and software. It improves 4%~1636% than the original one. Eventually, six complete test benches are executed on VM-based platform as well as on FPGA-based platform and gather the respective data for verification demand.
... Four benchmarks are used as case studies as shown inFig. 8. Benchmark 1 named " San Angeles Observation " [19] as can be seen inFig. 8 (a), which is a public domain OpenGL|ES 3D graphics video benchmark. ...
Power management is one of the key techniques in the design of portable multimedia devices. With the advent of faster advanced embedded processors and higher capacity storage media devices, mobile devices will be capable of handling the much functionality such as digital still camera (DSC), camcorder, audio player, and games, etc. This convergence in applications coupled with evolving consumer expectations and rapid development in embedded processor capabilities pose tremendous challenges. One of the many design challenges to be addressed in this fast growing segment is the even increasing demand for power hungry media processing functions to be offset with the demand for longer battery life.
Integration at the chip-level often combining the many processing cores and peripheral devices interface into a single chip exacerbates the power consumption problem. Therefore, power management no longer remains a hardware only problem and needs to be addressed at the system-level. Most existing techniques have limited themselves to hardware-based dynamic voltage and frequency scaling (DVFS) schemes. However, these techniques have not been designed well enough to be scalable to handle the many multimedia application states that the devices support. So there is a strong need to devise new system-level power management solutions that utilizes the DVFS to the best possible extent as application moves from one state to other.
In such demand, this research proposal proposes a unified power management mechanism for energy-aware low-power multimedia mobile devices that is capable of handling many multimedia applications with 3D graphics acceleration in a single mobile device and provides the best possible power optimization strategy suitable for each of the several multimedia applications supported in a mobile device.
... The PCM [4] collects real-time statistics of a 3DG application running in hardware, including the vertex rates, pixel rates, tile num- bers, memory access, bus idle/busy counts, and data transfer rates and conflict/busy/wait information of each bus master etc. The re- lated information of 3D graphics hardware execution can be provided by monitoring tool as summarized in Table I. ...
This paper presents an embedded debugging/performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based D graphics SoC development.
D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.
