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The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is compose...
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... TC dependence on the consumption, and the bottom Fig. 3 (b) shows the maximum voltage across the diode as a function of the diode bias current. Since our voltage refer- ence is designed for a 0.5 V supply voltage with low power consumption, and the design should target lower fabrication mismatch spread, we chose the 5x5 µm 2 diode biased at 1 µA. Fig. 4 shows the forward voltage across the 5x5 µm 2 Schottky diode biased at 1 µA, presenting a voltage drop from 390 to 140 mV in the temperature range from -55 to 125 °C, and around 280 mV at room temperature with and average CTAT temperature sensitivity of -1.45 mV/°C. For our low-voltage reference design, a low power PTAT current ...
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Citations
... In this paper, an ZTC-based integrated reference exploiting the approach outlined in [14] is demonstrated on silicon for the first time. Based on the ZTC theoretical modeling aspects reviewed herein, the reconfigurability of the final desired voltage reference by changing the PTAT current generator under the same device is also demonstrated. ...
... The reference voltages are obtained directly from the gatebulk voltages (V GS =V REF ) of M SVT , M LVT and M ZVT . Based on (4)-(6), i.e., after generated the bias current with a defined TC PTAT and found out the i f 0 , each diode-connected transistor in Fig. 2 can be properly designed and their aspect ratio can be obtained by the procedure reported in [14]. In particular, transistor aspect ratio W L can be expressed as a function of its inversion level i f [20] in (8) as: ...
A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3V up to 1.2V and outputs three different reference voltages using Standard-VT (SVT), Low-VT (LVT), and Zero-VT (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13-μm CMOS process show a worst-case normalized standard deviation (σ/μ) of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/∘C over the full commercial temperature range. At room temperature (25∘C), line sensitivity in the ZVT VR is just 1.3%/100mV, over the whole supply range. The proposed reference draws around 5 μW and occupies 0.014 mm2 of silicon area.
... The ZTC operating point is based on the mutual compensation of the temperature dependences of carrier mobility and threshold voltage [7]. It usually lies in the moderate or strong inversion region [8] and can be found in a plethora of CMOS technologies including advanced nodes such as 14-nm FDSOI [9]. Fig. 1 shows an example of an nMOS transistor with its drain fixed at 1 V in a 130 nm CMOS technology. ...
... For a better comparison, minimum length transistors have been used ensuring similar ZTC voltages. As explained in detail in Section IV, the nMOS in the 130-nm technology show a strong dependence of threshold voltage on channel length resulting in very different ZTC voltages between nMOS and pMOS transistors according to (8). From the same equation, it is also clear that the main source of process variation of the ZTC point stems from the threshold voltage. ...
... For the resulting circuit to be usable in a system, its output voltage must have sufficient margin with regard to both rails. From (8) it is clear that the ZTC voltage is primarily set by the threshold voltage. With a typical threshold voltage around 0.45 V for short channel transistors, the core devices of our targeted CMOS technology generally have a V G S F too high for ultralow voltage operation. ...
Most conventional CMOS technologies possess the so-called zero-temperature coefficient (ZTC) operating point where the transistor's drain current becomes nearly independent of temperature due to the mutual temperature cancellation of threshold voltage and carrier mobility. This paper discusses how this ZTC point can be exploited in the design of current and voltage references with low supply voltages. Besides a theoretical overview regarding the ZTC behavior, a current reference in a standard 0.25-μm CMOS technology operable from 1.3 V is presented. To further explore the possibilities of this approach, a voltage reference with a nominal supply voltage of just 0.5 V is designed and fabricated in a 130-nm technology. Measurement results are given for both circuits.
... This leaves room for two basic circuit concepts to realize a temperature-independent voltage: The transistor can be biased directly at its ZTC point, as e.g. in [6], or outside this point with a current source that shows the opposite temperature behavior compared to the gatesource voltage. In [7], a Shottky-based PTAT current source is used to bias an nMOS transistor. The design also employs zero-V th transistors. ...
... I the presented voltage reference is compared to other untrimmed ultra-low voltage designs. With respect to the circuits based on Shottky diodes, this work shows very good [4], exp [5], sim [15], exp [16], exp [3], exp [7], sim performance. The recently presented designs from [4], [5], and [15] based on a BGR with charge pumps or subthreshold MOSFETs, however, perform significantly better, especially in terms of power consumption. ...
This paper presents a voltage reference circuit operational from a 0.5 V supply which is based on the zero-temperature coefficient (ZTC) operating point of a MOS transistor. The ZTC condition is reviewed and it is found that a MOSFET biased below its ZTC point with a PTAT current source can yield a temperature stable output at this low supply voltage. With this idea in mind, a circuit which does not rely on the availability of special devices like Shottky diodes is designed in 130 nm CMOS. Simulations show that this circuit generates an average reference voltage of 318 mV from a 0.5 V supply. The temperature coefficient is 154 ppm/K and the voltage reference has a power supply rejection ratio (PSRR) of 41 dB at DC.
... Besides the above two classes, a third approach for achieving low-supply voltage operation is also possible. The [3][4]. Although the circuit proposed by [4] operates with very low VDD using Shottky diode, its large current consumption of more than 600 µA may be prohibitive for portable applications. ...
... where VDS4 is equal to (VGS2-VGS1), and is given by (3). Accordingly to [7], IREF is also given by: Parameter β is µ0*COX*W/L, and nc is a correction factor for low drain source voltages [7]. ...
This work presents the design of a new 1 V supply resistorless voltage reference using Schottky diode. The designed circuit also provides a temperature-compensated output current in nano-amper order. The nominal output voltage (VREF) and output current (IREF) are 741 mV and 15 nA, respectively. The total current consumption and the layout area are 500 nA and 0.011 mm 2 , respectively. The line regulation sensitivity for VREF and IREF are 0.5 mV/V and 29 pA/V, respectively. The power supply rejection ratio is-41 dB at DC for a supply voltage of 1.2 V. The circuit operates with a supply voltage from 2.5 V to 1.0 V. The temperature range used in simulations is-40 °C to 85 °C and the technology used in this work is a commercial 130 nm CMOS process. Index Terms-Shottky diode, Bandgap voltage reference, resistorless, current reference, low voltage supply.
... MOSFET ZTC condition derives from the mutual cancellation of mobility and threshold voltage dependencies on temperature, that happens at a particular gate-to-bulk voltage bias. The drain current ZTC operating bias point is defined in [6] and in other publications [5,[22][23][24], always based on strong inversion quadratic MOSFET model, which is a simplified approach. From [22], ZTC operating point is given by Eqs. ...
... Eqs. (5) and (6) relate the source and drain inversion coefficients (forward and reverse), i f ;r , with external applied voltages, V G , V S and V D , using the bulk terminal as reference. ...
... ZTCS shows that the minimum ZTC forward inversion level is around 15.6 for a l ¼ À2:5 and a V T0 ¼ À0:5°C. Since inversion coefficient i f ¼ 3 means the condition where V G ¼ V T0 from Eqs. (5) and (6), one can conclude that ZTC bias condition always occurs for gatebulk voltages larger than threshold voltage. ...
Electromagnetic interference (EMI) can significantly degrades the performance of analog circuits, including voltage and current references, especially due to their limited power supply rejection. An EMI resistant MOSFET-only voltage reference is herein proposed, based on the MOSFET zero temperature coefficient (ZTC) vicinity condition. The ZTC condition is analytically derived through a continuous MOSFET model that is valid from weak to strong inversion, also a design methodology is presented. The final circuit is designed in a 130 nm process and occupies around 0.0075 mm of silicon area while consuming just 10.3 \upmuW. Post-layout simulations present a 395 mV reference voltage () with a effective temperature coefficient () of 146 ppm/°C, for a temperature range from −55 to +125 °C. A 4 dBm (1 amplitude) EMI source injected into the power supply, according to direct power injection standard [1], results in a maximum DC Shift and peak-to-peak ripple of −1.7 % and 35.8 m, respectively. The proposed voltage reference has already been fabricated and is under preliminary measurements, presenting a maximum variation of 21 mV for a 600 mV minimum supply.
Giemsa dye was used as an interlayer film structure between Co metal and n-type silicon to fabricate Co/giemsa/
n
-Si heterostructure to determine various electrical behaviors. For that reason, temperature-dependent current voltage (
I-V
) and frequency-dependent capacitance voltage (
C-V
) measurements were employed to reveal electrical properties of the Co/giemsa/
n
-Si heterostructure for wide range temperature and frequency. Various junction parameters such as series resistance, barrier height and ideality factor values were determined from
I-V
characteristics by thermionic emission (TE), Cheung and Norde methods. The results revealed that the junction parameters were strong function of the measurement temperature. Frequency dependent
C-V
characteristics were also utilized for extraction of various electrical parameters such as maximum electric field, depletion width, barrier height etc. The results highlighted that all electrical parameters changed as function of the frequency and voltage. The Co/giemsa/
n
-Si heterostructure can be improved for thermal sensing and switching applications.
In this work, wide temperature range junction sensor was fabricated and comprehensively analyzed by grown of Graphene oxide (GO)-Fe3O4 blend on a p-type Si substrate via spin coating system. Cr was coated on GO-Fe3O4 with a DC magnetron sputtering. The temperature-dependent current–voltage (I–V) measurements of GO:Fe3O4/p-Si rectifying device were carried out in the temperature range of 100–400 K. The temperature sensitivity of the GO:Fe3O4/p-Si rectifying device was calculated for different forward current values and it was seen that the temperature sensitivity ranged from −1.18 mV/K (0.25 mA) to −1.08 mV/K (1.00 mA). Temperature-dependent I-V characteristics were explained by the thermionic emission (TE) theory by considering the presence of double Gaussian distribution of the barrier heights. It was observed that the barrier height and the ideality factor changed with temperature in accordance with the inhomogeneous barrier behavior. Ideality factor, series resistance and barrier height for the junction were calculated and analyzed. While the barrier height values varied between 0.20 eV (100 K) and 0.66 eV (400 K), the ideality factors varied between 5.81 (100 K) and 3.11 (400 K). In log(I)-T scale, the current varied approximately linearly with temperature at each temperature. Wide temperature range electrical measurements of GO:Fe3O4/p-Si rectifying device have showed that the device can be a temperature sensor due to its linear temperature dependent characteristics between 100 K and 400 K.
Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of electronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 μA. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0.010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (T Cef f ) of 15 ppm/o C from −45 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V . The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 μA under a supply voltage of 1.8 V, and occupying a silicon area around 0.010mm2. Results from circuit simulation show an T Cef f of 60 ppm/o C from -45 to +85 oC and a power consumption of 63 μW. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 μW. Post-layout simulations present a T Cef f of 146 ppm/o C, for a temperature range from −55 to +125o C. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp , respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a T Cef f of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125o C, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 μW. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/o C.
