Fabrication process flow: (a) Initial layer stack; (b) AlN wet etching; (c) Pt structuring; (d) Dry etching of silicon nitride and wet etching of silicon oxide, aluminum deposition; (e) backside structuring by DRIE; and (f) dry etching of device silicon. The adhesion of photoresists during the AlN wet etch process is not sufficient. Therefore, a 100 nm SiO 2 is the hard mask material for the patterning process. AlN and Al 0.68 Sc 0.32 N wet etching is done with 85% phosphoric acid solution (H 3 PO 4 ) at 80 • C (Figure 4b). The etch rate of AlN is 1.4 nm/s. The Al 0.68 Sc 0.32 N has a etch rate of 6.7 nm/s. Test wafer with Al 0.86 Sc 0.14 N have etch rates of 4.2 nm/s. This indicates a correlation of higher etch rates and higher Scandium ratios in the piezoelectric transducer. The platinum and titanium are structured via tungsten hard mask by a dry etch process (Figure 4c) which is monitored with an optical emission spectrometer. By analyzing the species in the plasma, an etch stop can be defined as soon as the Ti/Pt is etched and the dry etching of the silicon nitride starts. In Figure 4d, the silicon nitride is patterned by RIE and the silicon oxide is wet etched. This enables an aluminum deposition on a smooth silicon surface. The 800 nm aluminum layer serves as reflective layer on the mirror plate and as upper electrode for excitation of the piezoelectric actuators. After wet etching of the aluminum layer, the handle wafer silicon is structured by DRIE using the buried SiO 2 of the initial SOI wafer as etch stop (Figure 4e). By variation of the exposure parameters in the lithography as well as the DRIE parameters, a side wall shift of the silicon springs can be done to reduce the systems stiffness. This process can be done by using different resists, exposure times, or another DRIE process recipe. For the wafer with AlN this side wall shift is about 0.85 µm at each sidewall. This results in a change of the spring with from a = 5 µm to a = 3.3 µm. For the wafer with Al 0.68 Sc 0.32 N a side wall shift of 1.35 µm is used. The lower stiffness should result in higher deflection per voltage and further increase the MOEMS performance compared to systems with high resonance frequency.

Contexts in source publication

Context 1

... wafers with AlN and Al 0.68 Sc 0.32 N piezoelectric layers are processed with an identical process flow and process parameters, except for the deposition and etching of the piezoelectric material. Figure 4 illustrates the device fabrication process flow. The microsystem fabrication is based on 150 mm SOI technology with 575 µm thick handle wafer and 20 µm device-silicon thickness. ...

Context 2

... the case of Al 0.68 Sc 0.32 N, co-sputtering from 5N5 Al and 4N pure Sc targets in pulsed DC mode in 100% nitrogen atmosphere is used at combined power of 1000 W. AlScN growth optimization, as well as structural and compositional analysis are discussed elsewhere [15,16]. The platinum and titanium are structured via tungsten hard mask by a dry etch process (Figure 4c) which is monitored with an optical emission spectrometer. By analyzing the species in the plasma, an etch stop can be defined as soon as the Ti/Pt is etched and the dry etching of the silicon nitride starts. ...

Context 3

... analyzing the species in the plasma, an etch stop can be defined as soon as the Ti/Pt is etched and the dry etching of the silicon nitride starts. In Figure 4d, the silicon nitride is patterned by RIE and the silicon oxide is wet etched. This enables an aluminum deposition on a smooth silicon surface. ...

Context 4

... 800 nm aluminum layer serves as reflective layer on the mirror plate and as upper electrode for excitation of the piezoelectric actuators. After wet etching of the aluminum layer, the handle wafer silicon is structured by DRIE using the buried SiO 2 of the initial SOI wafer as etch stop (Figure 4e). ...