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FCC Spectral Mask for UWB Indoor Communication Systems

FCC Spectral Mask for UWB Indoor Communication Systems

Source publication
Technical Report
Full-text available
This work presents a higher derivative Gaussian pulse generator using an enhanced amplitude modulator with a differential connected load. The aim of the design was to obtain a high amplitude Gaussian pulse with low power consumption. Our contribution in this thesis is the amplitude modulator which provided pulse shaping and resistive feedback curre...

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... fractional bandwidth is defined as 2(fH-fL)/(fH+fL), where fH and fL are the upper and lower frequencies, respectively, measured at -10 dB below the peak emission point. To allow government and industry to conduct UWB testing, frequency spectrum from 3.1GHz to 10.6GHz was allocated for communications use below specified power levels, while imaging was limited to below 960 MHz, as seen in Figure 2 below. A significant amount of testing will be performed to calculate the amount of interference that UWB causes to narrowband signals. ...
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... inverting buffer as a current amplifier can generate sufficient current to drive the differential load. As the widths of NMOS and PMOS are quite large in CMOS inverting buffer circuits, generally they have high power consumption and swift transition in unloaded condition according to Voltage Transfer Characteristic (VTC) displayed in Figure 20. As output signals from previous AM blocks have ripples near Vdd, CMOS inverter buffers consider these ripples as noise and invert to 0V. ...
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... VZ will be higher than 0V when VD is Vdd. So, Incorporation of feedback resistor creates slower voltage transition and also lowers output voltage headroom in unloaded condition according to VTC given in Figure 20. Lower the feedback resistance, voltage transition is slower and output voltage range is lower. ...
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... 2 represents simulation results from the proposed generator. Output pulses with their corresponding PSD with outdoor FCC mask are observed in Figure 22. Figure 22: Output swing and corresponding PSD for 3rd to 7 th derivative Gaussian pulse Figure 23: Output swing and corresponding PSD for 8th to 11th derivative Gaussian pulse Table 3 summarizes the comparison of the key specification among this design and with previously reported pulse generators. ...
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... 2 represents simulation results from the proposed generator. Output pulses with their corresponding PSD with outdoor FCC mask are observed in Figure 22. Figure 22: Output swing and corresponding PSD for 3rd to 7 th derivative Gaussian pulse Figure 23: Output swing and corresponding PSD for 8th to 11th derivative Gaussian pulse Table 3 summarizes the comparison of the key specification among this design and with previously reported pulse generators. It shows that the proposed pulse generator is c= calculated from the literature data a=calculated from the literature figure ...
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... 2 represents simulation results from the proposed generator. Output pulses with their corresponding PSD with outdoor FCC mask are observed in Figure 22. Figure 22: Output swing and corresponding PSD for 3rd to 7 th derivative Gaussian pulse Figure 23: Output swing and corresponding PSD for 8th to 11th derivative Gaussian pulse Table 3 summarizes the comparison of the key specification among this design and with previously reported pulse generators. It shows that the proposed pulse generator is c= calculated from the literature data a=calculated from the literature figure ...
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... observation has been made while fitting those waveforms in the FCC mask with maximum amplitude and minimum pulse width. According to Figure 25, increment in the order of Gaussian pulses increases Vpp and PW (from 3rd order to 7th order) and remains more or less unchanged (from higher than 7th order). High voltage swing and low pulse width are important performance parameters of any Gaussian pulse generator. ...
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... voltage swing and low pulse width are important performance parameters of any Gaussian pulse generator. Figure 24 offers the highest peak voltage and lowest pulse width requirement for any higher order Gaussian pulse within FCC mask. Vpp/PW (Ratio of Output swing to pulse width) gives a better overview of which derivative of Gaussian pulse can provide best performance based on this parameter. ...
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... (Ratio of Output swing to pulse width) gives a better overview of which derivative of Gaussian pulse can provide best performance based on this parameter. In Figure 24, 7 th derivative Gaussian pulse gives better result according to simulation. So for this design we opted for 7 th derivative pulse generator using Edge combiner and Pulse combiner circuit blocks from general architecture. ...
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... schematic of the proposed UWB PG that receives clock pulse to generate 7th derivative Gaussian pulse is shown in Figure 26. The designed PG consists of voltagecontrolled inverted delay lines (VCIDL), impulse generators, edge combiner circuits for forming combined unmodulated pulse. ...
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... of using a higher number of inverters, VCIDL is utilized for synthesizing 9 delayed inverted pulses from the input clock signal presented in Figure 27(a). A current mirror circuit with a control voltage VC is employed to generate a constant current which drives the upper and lower MOSFETs of the current starved VCIDLs in saturation mode with a constant current. ...
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... current mirror circuit is optimized for low power consumption because it consumes power during idle state too. The delayed inverted pulses for VC=580mV is shown in Figure 27(b). ...
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... impulse generator generates short pulses for low duty cycle operation and low power consumption shown in Figure 28. Passing a positive triggered signal and the corresponding delayed negative triggered signal of the previous signal through an AND gate develops a positive impulse (Dis_even). ...
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... negative impulse (Crg) is the inverted signal of the corresponding positive impulse (dis). The positive and negative impulse signals are provided in Figure 29. ...
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... clock signal and Do5 as input, a pulse HP is synthesized through a NAND gate. HP is used as an input in the inverter displayed in figure 32, which is adopted to form a triangular pulse. The delay time depends on the transistor size and capacitance of Cm. ...
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... inverting buffer as a current amplifier can generate sufficient current to drive the differential load. As the widths of NMOS and PMOS are quite large in CMOS inverting buffer circuits, generally they have high power consumption and swift transition in unloaded condition according to Voltage Transfer Characteristic (VTC) displayed in Figure 20. As output signals from previous AM blocks have ripples near Vdd, CMOS inverter buffers consider these ripples as noise and invert to 0V. ...
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... VZ will be higher than 0V when VD is Vdd. So, Incorporation of feedback resistor creates slower voltage transition and also lowers output voltage headroom in unloaded condition according to VTC given in Figure 20. Lower the feedback resistance, voltage transition is slower and output voltage range is lower. ...