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![Experimental measurements [6] and the semi-log scale plot of the modelling results I–V characteristics with D = 4 nm.](publication/283649867/figure/fig2/AS:11431281307612072@1738694026876/Experimental-measurements-6-and-the-semi-log-scale-plot-of-the-modelling-results-I-V.jpg)
Experimental measurements [6] and the semi-log scale plot of the modelling results I–V characteristics with D = 4 nm.
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This paper presents a novel mathematical model of the bipolar resistive switching (BRS) of the metal-insulator-semiconductor-metal (MISM) in a Pt/Ta2O5/TaOx/Pt memristor. The proposed model is based on quantum mechanics and describes the BRS behaviour based on electron band theory and the physical characteristics of the metal-insulator-semiconducto...
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A key step in engineering resistive switching is the ability to control the device switching behavior. Here, we investigate the possibility to tune the resistive switching of tantalum oxide (TaOx)-based memristors from a non-switchable state to a switchable state by applying post-fabrication annealing of the devices. The switching of the devices wa...
A memristor is defined as a non-volatile memory switching two-terminal resistor, and a memristor with digital switching characteristics is widely studied as a next-generation non-volatile memory because of its simple structure, high integration density, and low power consumption. Recently, analog memristors with gradual resistance switching (RS) ch...
Citations
... Similarly, SRAMs suffer from increased leakage current when scaled up [5]- [7]. The emerging non-volatile memory technologies such as phase-change memory (PCM) [8], ferroelectric memory [9], resistive random access memory (RRAM) [10]- [12] are potential contenders to replace the aforementioned matured technologies. RRAMs can potentially offer higher memory densities; faster read/write speeds, and lower power dissipation [13], [14]. ...
... Resistive random-access memory (RRAM) is a futuristic technology that can be used as in-memory computing and in storage memory [1][2][3][4][5]. Even though this technology is promising with its nanoscale dimension as well as low power operations, the major challenge is the sneak path current originate due to low resistive paths provided by the unselected memory cells in the crossbar array (CBA) [6,7]. ...
... Further, different top electrode metals and dielectric materials to demonstrate the formation of an optimal stack for the desired application the selector model is performed. Then the developed selector device model is integrated with an analytical model of oxygen vacancy-controlled RRAM device [1,28] forming a 1S-1R analytical model. However, the acquired features of the presented 1S-1R model demonstrate the effective mitigation of the sneak path current in a CBA. ...
... When the input voltage is applied on the multi-layered device, the total electric field distributes across the resistive dielectric layers based on their dielectric constants and layer thickness. This relation between electric field, dielectric constant and layer thickness can be derived with Gausses' law as in (1), where E 1 is the electric field, D Ta 2 O 5 is the thickness of the top insulator and D TiO 2 is the thickness of bottom insulator [29], ε denotes the permittivity of the dielectric materials. From the simulation, it has been noticed that most of the field appears across the Ta 2 O 5 /TaO x layer [30], and the distribution of electric potential across the insulating layers is given by Kirchhoff's voltage law as given in (2), where E TiO 2 is the electric field across the bottom oxide ...
One selector‐one resistor (1S‐1R) configuration is desirable to use in conductive bridge resistive random‐access memory (CBRAM) and resistive random‐access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S‐1R to reduce the sneak path current. The proposed selector model is developed by considering the electric field‐driven tunnelling mechanisms co‐exist in thin multi‐layer devices such as direct and Fowler‐Nordheim tunnelling. The simulated characteristics of proposed model shows high non‐linearity (∼1600), high selectivity (∼10⁴), high current density (∼10⁷ A/cm²) and low off current (∼46 nA). Further, the proposed model is simulated with different top electrode metals and dielectric materials to demonstrate the formation of optimal stack for the desired application. Then, the proposed selector model (1S) is integrated with RRAM model (1R) and the compatibility of the devices is verified. Moreover, from the presented 1S‐1R model, various parameters for the establishment of CBA such as read/write voltages for selected/unselected trails are predicted and substantial conditions for sneak path current reduction such as non‐linearity, Roff/Ron ratio and off‐current (10 nA) are also evaluated.
... Therefore, the V o accumulation creates a conducting filament (CF) [25][26][27]. This CF forms a conduction path for electrons to travel from TE to BE and the device readily attains its LRS [28]. Application of positive voltage on the top electrode causes movement of oxygen ions from bottom to top layer of the Zr x Hf 1-x O 2 devices and is shown in Fig. 5(d) and (e). ...
... In this process the temperature in the channel is also increased. A recombination with oxygen vacancies takes place for such movement at high temperature that in turn shrinks CF and thus memory device leads to HRS [28]. ...
The effect of Zr content on resistive switching properties of ZrxHf1−xO2- based metal-oxide-semiconductor (MOS) devices has been studied. The electrical characteristics and x-ray photoelectron spectroscopy studies reveal that the resistive switching property performs its best when the Zr content in the film is 9.11%. The XPS data reveals presence of non-lattice oxygen in all the devices. The differential scanning calorimetry (DSC) study shows an endotherm peak at ~ 145.9 ◦C only for the sample at a particular Zr content in the ZrxHf1−xO2 film indicating release of lattice oxygen. Thus, besides presence of non-lattice oxygen in the film, further generation of hole trap density in the form of lattice oxygen release is required to achieve a better low resistance state (LRS) and the same is reflected in the double logarithmic plot of I − V . It is believed that some sort of microstructural arrangements take place at a critical Zr content that lead to the lowest resistive state of the MOS device.
... In a large density RRAM array, sneak path current has a drastic effect on the state of unselected RRAMs and can result in a bit flip. Amongst the methods to overcome this 978-1-7281-0460-7/19/$31.00 ©2019 IEEE drawback are device engineering to produce desirable behaviour [9], implementing a 1 transistor-1 RRAM (1T1R) configuration [10], implementing a switch-like selector in series with the RRAM (1S1R configuration) [11], or designing a circuit that can overcome this limitation. Device engineering does not fully eliminate the device variability and further behavioural engineering requires additional material or specific structural changes which increases cost and fabrication complexity [12]. ...
... Two terminal SPICE circuit models with TAT and GTAT are realized in circuit level by implementing the additional voltage dependent current sources in existing two terminal circuit model of the device [8], [17]. In the existing device model, the current conduction is modelled with Schottky barrier tunneling while, the state dynamics is modelled with the existance of oxygen vacancies present at the conduction filament as given in Fig. 1 where, the capacitor Cw and resistor R take values as in [8]. ...
... Further studies on engineering the material and structure of RRAMs to fine-tune its performance have been performed [5,6] and RRAMs can now be further categorised by its structure and the resistive switching characteristics. RRAMs can be divided into two categories, oxide-based RRAMs (OxRAM) [7] and conductive bridge RRAMs (CBRAM) [8,9] depending on the mechanism behind their RS behaviour. ...
This article presents a review of physical, analytical, and compact models for oxide-based RRAM devices. An analysis of how the electrical, physical, and thermal parameters affect resistive switching and the different current conduction mechanisms that exist in the models is performed. Two different physical mechanisms that drive resistive switching; drift diffusion and redox which are widely adopted in models are studied. As for the current conduction mechanisms adopted in the models, Schottky and generalised hopping mechanisms are investigated. It is shown that resistive switching is strongly influenced by the electric field and temperature, while the current conduction is weakly dependent on the temperature. The resistive switching and current conduction mechanisms in RRAMs are highly dependent on the geometry of the conductive filament (CF). 2D and 3D models which incorporate the rupture/formation of the CF together with the variation of the filament radius present accurate resistive switching behaviour.
... Another type of resistive switching process incorporates the tunnelling probability factor (TPF) between the semiconductor and the metal layers, which is based heavily on Schottky barrier modulation and tunnelling, where the majority charge carrier is electrons. Resistive switching behaviour based on Schottky barrier modulation differs from the conducting channel theories, but these switching behaviour have also been proven to be correct [97]- [99] and the memristor modelling for these type of switching process for MISM memristor devices has also been proposed [100]. However, at the time of this research, the conducting channel theory was used for memristor modelling due to the lack of MISM memristor models and memristor models that are based on the modulation of Schottky barrier. ...
This dissertation reports the research work that was conducted to propose a non-volatile architecture for FPGA using resistive switching devices. This is achieved by designing a Configurable Memristive Logic Block (CMLB). The CMLB comprises of memristive logic cells (MLC) interconnected to each other using memristive switch matrices. In the MLC, novel memristive D flip-flop (MDFF), 6-bit non-volatile look-up table (NVLUT), and CMOS-based multiplexers are used. Other than the MDFF, a non-volatile D-latch (NVDL) was also designed. The MDFF and the NVDL are proposed to replace CMOS-based D flip-flops and D-latches to improve energy consumption. The CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the MDFF provides switching speed of 1.08 times faster; the NVLUT reduces power consumption by 6.25nW and improves device area by 128 transistors; while the memristive logic cells reduce overall device area by 60.416μm2. The NVLUT is constructed using novel 2TG1M memory cells, which has the fastest switching times of 12.14ns, compared to other similar memristive memory cells. This is due to the usage of transmission gates which improves voltage transfer from input to the memristor. The novel 2TG1M memory cell also has lower energy consumption than the CMOS-based 6T SRAM cell. The memristive-based switch matrices that interconnects the MLCs together comprises of novel 7T1M SRAM cells, which has the lowest energy-delay-area-product value of 1.61 among other memristive SRAM cells. Two memristive logic gates (MLG) were also designed (OR and AND), that introduces non-volatility into conventional logic gates. All the above circuits and design simulations were performed on an enhanced SPICE memristor model, which was improved from a previously published memristor model. The previously published memristor model was fault to not be in good agreement with memristor theory and the physical model of memristors. Therefore, the enhanced SPICE memristor model provides a memristor model which is in good agreement with the memristor theory and the physical model of memristors, which is used throughout this research work.
... In [11], the electron tunnel barrier model [9] is modified to avoid non-convergence, numerical errors, and non-physical solutions during time-domain simulation. Also, two physics-based models have been proposed recently for TaO x -based devices [12,13]. The model in [12] considers TaO x -based devices with a circuit model that consists of a Schottky barrier diode in low resistance state, a variable resistor, and a base-layer resistor. ...
... The model in [12] considers TaO x -based devices with a circuit model that consists of a Schottky barrier diode in low resistance state, a variable resistor, and a base-layer resistor. In [13], modeling is based on incorporating the tunneling probability factor between the metal layers and the semiconductor layer, and demonstrating its effect on the conduction mechanism. ...
Memristors have the potential to significantly impact the memory market, and have demonstrated the potential for analog computing within a sub-class of neuro-inspired information processing. In order to enable circuit designers to use and test memristor/CMOS hybrid circuits, it is necessary to have an accurate and reliable memristor model. In this work, a new memristor model based on Charge Transport Mechanism (CTM) is presented. This paper analyzes different current mechanisms that exist in Schottky barrier region of memristors: direct tunneling, thermionic emission, and Ohmic currents. The proposed memristor model is based on direct tunneling and Ohmic conduction, and it accounts for physical phenomena within memristive devices. The presented model shows a relative root mean square error of about 0.25 when compared with experimental results for a Ag/TiO2/ITO memristor. It also shows better accuracy in comparison with other modeling approaches published in the literature. The proposed model is implemented in SPICE and a subcircuit for the model is provided.
... Real memristive devices usually comprise several nonvolatile and volatile switching mechanisms [10], which require a higher order of the differential equation of motion. This class includes model [22] and more recent works [23][24][25] for TiO 2 , WO x , and TaO x memristors. ...
The paper deals with the modeling of memristors operating in extremely large memristive networks such as crossbar structures for memory and computational circuits, memristor-based neural networks or circuits for massively parallel analog computations. Because the non-convergence and other numerical problems increase with increasing complexity of the simulated circuit, suitable models of the individual memristors need to be choicely developed and optimized. Three different models are considered, each representing a specific trade-off between speed and accuracy. Benchmark circuits for testing the applications of various complexities are used for the transient analysis in HSPICE. It is shown how the models can be modified to minimize the simulation time and improve the convergence. Copyright
... Typical bi-layered RRAM device comprises a bulk layer and a more resistive switching (RS) oxide layer, sandwiched between two metal electrodes [3]. Different RS oxide materials have been reported for the bi-layered RRAM such as: AlO x /WO x [14], CuO/ZnO [15], HfO x /AlO x [16], [17], TiO x /HfO x [18], and Manuscript [2], [3], [8]- [13]. Among these materials, Ta 2 O 5 is considered as one of the prospective RS materials due to its high performance and the stable phases of TaO x and Ta 2 O 5 [19], [20]. ...
... A. Related Work 1) MIM RRAM SPICE Models: From the literature, it can be seen that a great progress has been made on the SPICE modeling of the MIM RRAM devices [21]- [26], and an evaluation criteria has been introduced in [27] which can be used to check the applicability of the these models and the MISM RRAM models to simulate the RS behavior. While these models are computationally efficient and showed good agreement with the measured data, the physics behind the behavior of the Ta 2 O 5 /TaO x bi-layered RRAM has not been fully covered in these MIM models [13] and each of these models showed different characteristics when compared to the Ta 2 O 5 /TaO x bilayered RRAM. Hence, the MIM RRAM models cannot be applied directly to the Ta 2 O 5 /TaO x bi-layered RRAM. ...
... The model in [16] is mainly utilized to elucidate the RS evolution in the RESET process without modeling the current conduction. The model in [17] is based on the metallic-like and the hopping conduction which is different from the Schottky barrier mechanism used for the Ta 2 O 5 /TaO x RRAM [2], [3], [13]. The conduction in AlO x /WO x RRAM is investigated in [14] where Schottky emission model does not take into account the possible tunneling, the effect of the continuous variation of the interface traps, and the image force lowering which is different from Ta 2 O 5 /TaO x RRAM [13]. ...
Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the Ta 2 O 5 /TaO x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from Pt/Ta 2 O 5 /TaO x /Pt RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of <; 11% and a maximum error of <; 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into Ta 2 O 5 /TaO x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the Ta 2 O 5 /TaO x bi-layered RRAM device performance at circuit level.
