Fig 2 - uploaded by Clifford Wolf
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Example interconnect with seven switches in three levels connecting nine cells of varying cell types
Source publication
Low power consumption or high execution speed is achieved by making an application specific design. However, today's systems also require flexibility in order to allow running similar or updated applications (e.g. due to changing standards). Finding a good trade-off between reconfigurability and performance is a challenge. This paper presents a too...
Contexts in source publication
Context 1
... the implementation of the reconfigurable modules, the tree topology was chosen to connect the individual cells due to its advantages and that it fulfils the above defined requirements. The interconnect is a tree (see Fig. 2) with the cells as leaf nodes and reconfigurable switches as inner nodes as well as the edges as connections (electrical ...
Context 2
... switches are unidirectional circuits which can be con- figured to connect any input port to any output port (see the detail in Fig. 2). The degree of a switch is the number of its children, (e.g., Switch 3 has a degree of two, Switch 6 has a de- gree of three). Each cell and each switch have a parent switch, except the top-most root switch. The height of the tree is the number of levels (e.g., Fig. 2 has a height of ...
Context 3
... con- figured to connect any input port to any output port (see the detail in Fig. 2). The degree of a switch is the number of its children, (e.g., Switch 3 has a degree of two, Switch 6 has a de- gree of three). Each cell and each switch have a parent switch, except the top-most root switch. The height of the tree is the number of levels (e.g., Fig. 2 has a height of ...
Context 4
... (for input and output purposes or distributing global signals such as clock and reset). It is also possible to embed configuration data for reconfigurable cells (ALUs, etc.) within the InterSynth con- fig bitstream. Inputs and outputs to the whole reconfigurable modules are handled as special cell types and therefore are not explicitly drawn in Fig. 1 and 2. The automatically generated interconnect shown in Fig. 3 only has one input and one output labeled IN[0] and OUT ...
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Citations
... The performance only needs to be sufficient for protocol implementation, making the trade-off between fewer resources and speed. To achieve this goal, a new processor called Baby8, designed for FPGA I/O, is being developed using Yosys Synthesis software version 0.38 [1,2]. ...
The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small "soft-core" processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources, including program size for 8-bit applications. The number of instructions is not large, but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2 mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.
Low power consumption or high execution speed is achieved by making an application specific design. However, today's systems also require flexibility in order to allow running similar or updated applications (e.g. due to changing standards). Finding a good trade-off between reconfigurability and performance is a challenge.This work presents a design methodology to generate application-domain specific heterogeneous coarse-grain reconfigurable architectures. The specification of the reconfigurable architecture is given by a set of example applications which define the whole range of its required functionality. These applications are analyzed to extract common building blocks, which can be reused between them.In the next step, the circuits of the application are merged to a single reconfigurable module. The major part of this work describes the according tool and its algorithm. Its main task is to optimize the interconnect by hierarchically grouping the functional units. Additional resources can be added to enable future applications. The tool generates the HDL source for a module with the instances of all blocks and the reconfigurable interconnect.The feasibility of the methodology is demonstrated by the design of reconfigurable architectures for digital filters as well as simple logic networks.
