Figure 3 - available via license: CC BY
Content may be subject to copyright.
Demonstration of the removal of surface defects by bias application. (a-c) STM images on an InAs nanowire approximately 200 nm from the biased contact, showing the {1010} facet with a stacking fault (SF)and numerous point defects and surface features. We probe filled states, with As surface atoms appearing as bright protrusions. All images were taken at V b = 0. On (a), label 1) is a mobile cluster of surface In atoms, 2) an As vacancy defect. (b) Imaging the same position at V b = 0 V after 6 scans over one hour at zero applied bias across the nanowire with little tip-induced motion of vacancies. (c) Imaging at V b = 0 V after V b = −2 V had been applied for 10 min, showing substantial motion and elimination of surface point defects. The nanowire growth direction (y, long axis of the nanowire) across which the potential is applied is indicated by an arrow. In all three images both vacancies and adsorbates can be clearly identified (example indicated by blue arrow) even though tip images conditions changed slightly. However, in the third image many defects present previously were no longer visible (example indicated by red arrow). Here V tip = −1.5 V in constant current mode at setpoint 80 pA.
Source publication
As semiconductor electronics keep shrinking, functionality depends on individual atomic scale surface and interface features that may change as voltages are applied. In this work we demonstrate a novel device platform that allows scanning tunneling microscopy (STM) imaging with atomic scale resolution across a device simultaneously with full electr...
Contexts in source publication
Context 1
... these measurements we chose to apply the bias and then image at V b = 0 in order to fully and unambiguously distinguish the effect of applied bias from the effect of tip scanning on the sur- face, which could otherwise potentially generate and rearrange defects independently to the applied bias. Figure 3a) shows the first image in one session of such STM imaging with a high resolution image taken on the {1010} facet on an InAs nanowire. We observe an unreconstructed flat surface with the same quality as in previous STM studies of grounded InAs nanowires on an InAs substrate 28 . ...
Context 2
... defect dynamics requires imaging stability which we tested by scanning the same area of the surface repeatedly for more than 1 hour with no bias along the nanowire. Figure 3b) shows the same position after this period of continuous scanning at V b = 0 V. At V b = 0 V the small point defect vacancies and the stacking fault do not alter. ...
Context 3
... after this period of continuous scanning at V b = 0 V. At V b = 0 V the small point defect vacancies and the stacking fault do not alter. Only a few mobile clusters of atoms on the surface moved. After checking that the tip did not significantly influence surface structure, a bias of V b = −2 V was applied along the wire for 10 min. The image in Fig. 3c) taken at V b = 0 V after this period shows the dramatic effect of the applied bias. The defect density was significantly reduced with many point defects now absent (example indicated by red arrow). The stacking fault remained essentially unal- tered, but two vacancies in it were eliminated along with several larger adsorbate features. ...
Citations
... This can be due either to a reduced amount of Cl − ions, which have migrated to the area underneath the source electrode under applied bias and have not moved back when removing the bias, or to a reduced amount of surface vacancies, which limited the initial Br XPS signal, but became partially filled with Br − ions upon device operation, similar as reported for an InAs NW device. 68 Combining the information from the local distribution of the binding energy and from the Br intensity behavior upon applying and removing an external bias, we come to the following conclusions: charged defects at the axial NW interface (leading to a strongly local in-built potential distribution) and surface vacancies can be healed by NW device operation at about 1.5 V. On the other hand, ion migration is observed already upon 0.5 V applied bias, which turns out to be partly irreversible after device operation at 1 to 2 V. ...
Metal-halide perovskites (MHPs) have gained substantial interest in the energy and optoelectronics field. MHPs in nanostructure forms, such as nanocrystals and nanowires (NWs), have further expanded the horizons for perovskite nanodevices in geometry and properties. A partial anion exchange within the nanostructure, creating axial heterojunctions, has significantly augmented the potential applications. However, surface degradation and halide ion migration are deteriorating device performance. Quantitative analysis of halide metal concentration and mapping of the electrical surface potential along the operating NW device are needed to better understand ion transportation, band structure, and chemical states, which have not been experimentally reported yet. This requires a characterization approach that is capable to provide surface-sensitive chemical and electrical information at the subμm scale. Here, we used operando nanofocused X-ray photoelectron spectroscopy (nano-XPS) to study CsPbBr3/CsPb(Br1–xClx)3 heterojunction NW devices with a spatial resolution of 120 nm. We monitored Br– and Cl– ion migration and comprehended the potential drop along the device during operation. Ion migration and healing of defects and vacancies are found for applied voltages of as low as 1 V. We present a model delineating band bending along the device based on precise XPS peak positions. Notably, a reversible redox reaction of Pb was observed, that reveals the interaction of migrating halide ions, vacancies, and biased metal electrodes under electrical operation. We further demonstrate how X-ray-induced surface modification can be avoided, by limiting exposure times to less than 100 ms. The results facilitate the understanding of halide ion migration in MHP nanodevices under operation.
... STM/S studies of NWs have become more common. [15][16][17][18][21][22][23] While a number of STM studies exist on nanowire {110} and {11-20} side facets, 15,17,18,[24][25][26][27][28] {001} facets of laterally grown III-V semiconductor NWs have not been studied by STM yet. In particular, there are only a few studies found for NW devices. ...
... In particular, there are only a few studies found for NW devices. [21][22][23] The In x Ga 1Àx As NW devices were selectively, laterally grown on a semi-insulating InP:Fe (001) substrate by MOVPE as described previously 9 and in the supplementary material. Schematic illustrations of the device are shown in Fig. 1. ...
... This has previously been sufficient to clean InAs and GaAs NWs. [15][16][17][21][22][23] After the cleaning, the sample was inserted into the LT-STM where a temperature of 10 K was reached in about 15 min. ...
Laterally grown InxGa1xAs nanowires (NWs) are promising candidates for radio frequency and quantum computing applications, which, however, can require atomic scale surface and interface control. This is challenging to obtain, not least due to ambient air exposure between fabrication steps, which induces surface oxidation. The geometric and electronic surface structures of InxGa1xAs NWs and contacts, which were grown directly in a planar configuration, exposed to air, and then subsequently cleaned using atomic hydrogen, are studied using lowtemperature scanning tunneling microscopy and spectroscopy (STM/S). Atomically flat facets with a root mean square roughness of 0.12 nm and the InGaAs (001) 4 2 surface reconstruction are observed on the top facet of the NWs and the contacts. STS shows a surface bandgap variation of 30 meV from the middle to the end of the NWs, which is attributed to a compositional variation of the In/Ga element concentration. The well-defined facets and small bandgap variations found after area selective growth and atomic hydrogen cleaning are a good starting point for achieving high-quality interfaces during further processing.
... InSb crystals have been increasingly investigated in order to develop low band gap (~0.2 eV) and high electron mobility (~80 000 cm 2 V −1 s −1 ) demanding electronics devices, but also various prospective future applications. For example, InSb is utilized nowadays in infrared detectors and is very potential for high-speed transistors operating at low voltages [1][2][3][4][5][6] and other ultra thin device applications 7,8 , and very recently, e.g., as building blocks of quantum computers 9 and THz transport waveguides 10 . The common challenge in developing these various InSb-based devices is how the surface or interface properties of InSb crystals can be modified in controlled manner. ...
... This is the same method we have used previously for preparing crystalline oxidized III-V(100) surfaces 14 , found to reduce the amount of defect states by over an order of magnitude beneath an atomic layer deposition (ALD) grown oxide film 15 and thus enabling efficient passivation. However, the following crucial questions have previously remained unresolved: (i) is the crystalline oxidation possible for other crystal planes; in more general for various crystal faces [not only (100) planes] exposed in nanotechnology 2,[7][8][9]12,16,17 , and (ii) how to produce clean InSb surfaces in an industrially potential way, which is necessary in order to perform the crystalline pre-oxidation in practice. Here we provide solutions to these questions using InSb(111)B as a template for investigations. ...
Oxidation treatment creating a well-ordered crystalline structure has been shown to provide a major improvement for III-V semiconductor/oxide interfaces in electronics. We present this treatment's effects on InSb(111)B surface and its electronic properties with scanning tunneling microscopy and spectroscopy. Possibility to oxidize (111)B surface with parameters similar to the ones used for (100) surface is found, indicating a generality of the crystalline oxidation among different crystal planes, crucial for utilization in nanotechnology. The outcome is strongly dependent on surface conditions and remarkably, the (111) plane can oxidize without changes in surface lattice symmetry, or alternatively, resulting in a complex, semicommensurate quasicrystal-like structure. The findings are of major significance for passivation via oxide termination for nano-structured III-V/oxide devices containing several crystal plane surfaces. As a proof-of-principle, we present a procedure where InSb(111)B surface is cleaned by simple HCl-etching, transferred via air, and post-annealed and oxidized in ultrahigh vacuum.
The physical and chemical properties of semiconductor nanowires are significantly influenced by their surface structure and morphology. This can be understood in that surfaces make out a much larger part of the total structure as compared to macroscale objects. An immediate consequence is that the lack of surface control can result in poor performance and reproducibility of any nanowire device. It is clear that bad performance is problematic, but it must be stressed that without performance reproducibility across millions of nanowires they can never become a useful real technology. This is indeed why many promising nanostructures and materials lost interest of both the scientific and commercial communities. However, surface control also can be used to strongly enhance nanowire performance and even introduce new functionality. As a result, surface functionalization is a key issue for nanowire science and technology. In this chapter, we describe in detail how standard surface science techniques such as Scanning Tunneling Microscopy (STM) and X-ray Photoemission Spectroscopy (XPS) can be modified for effective studies of 1D nanowires despite that they have been originally invented only for large and flat 2D surfaces. We go on to give a number of examples on how these techniques have revealed the precise structure–function relationship in particular of III–V semiconductor nanowires and their surfaces. We further discuss, how this can be used to control the structure and chemistry of the wires down to the atomic scale enabling new functionality for (opto)electronics, sensors, and many other device types. While we focus on III–V nanowires, the examples and techniques put forward should be applicable to many other material systems and types of nanostructures.
Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.
