DPCU electronics architecture block diagram.

Context in source publication

Context 1

... COMMON area hosts all the circuits necessary for the lines impedance matching and the management of the interfaces which are common to both the HOT and COLD sections. As shown in Figure 2, the electronics of the HOT (COLD) areas are based on a Zynq XC7Z7045 Xilinx (XC7Z045-L2FFG900I) System on Chip (SoC) flanked by a MICROSEMI ProASIC3E (A3PE) FPGA. The Xilinx SoC performs the task of control and processing unit while the FPGA has the task of managing the boot of the SoC and performing the role of WatchDog (WD) of the SoC, verifying its correct functioning. ...