D-Transform processing time comparison for 256x256 RGB image.

D-Transform processing time comparison for 256x256 RGB image.

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In this paper we will discuss the utilization of a set of waveforms derived from chaotic dynamical systems for compression and feature recognition in digital images. We will also describe the design and testing of an embedded systems implementation of the algorithm. We will show that a limited set of combined chaotic oscillations are sufficient to...

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... They provide implementations for the power converter algorithm in C, MATLAB and VHDL to show HLS competitiveness. Several other studies in the literature follow this approach such as the work by Hiraiwa and Amano (2013), Monson et al. (2013), Homisirikamol and Gaj (2014), Loughlin et al. (2014) and Glenn et al. (2013). ...
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Programming FPGAs requires advanced hardware design skills which limits their adoption in data centres. FPGA vendors have provided high level synthesis (HLS) tools to build register transfer level (RTL) specifications from designs provided in high level languages. We present a suite of C and C++-based hardware accelerators for the Purdue MapReduce benchmark suite and use the Xilinx Vivado HLS tool to compare their performance and resource efficiency to hand-coded RTL code. We show that simple design changes in the high level language-based accelerators can improve results. Using Vivado HLS, five benchmarks match the performance of hand optimised RTL while sort, self join, adjacency list and word count algorithms are about 4.7×, 3×, 2× and 1.3× slower, respectively.