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![Crux router; blue lines are waveguides and circles are microring resonator [12]](publication/308042800/figure/fig12/AS:405901015044101@1473785751355/Crux-router-blue-lines-are-waveguides-and-circles-are-microring-resonator-12.png)
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![Figure 3: Electronic switching fabric [25]](publication/308042800/figure/fig13/AS:405901015044105@1473785751629/Electronic-switching-fabric-25_Q320.jpg)
Photonic Network-on-Chips is a new generation of Network-on-Chips and has been proposed as a novel solution for the communication infrastructure of chip multiprocessors as well as a different solution to eliminate limitations of Network-on-Chips. Photonic Network-on-Chips has important properties such as increasing communication bandwidth, lowering...
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... This will result in the advent of a vital hindrance, namely, the universal intra chip communications substructure. Here, the most important step to be taken is the challenge in future systems to realize vast bandwidths and correct latency needs, especially when the number of processing cores also increases [4,23]. ...
... A plethora of studies focus on intrachip global communication via packet-switched micro-networks. These present a shared medium that is pretty scalable and gives ample bandwidth to substitute common bus-based links [4,36]. Yet, performance-per-watt is the most vital design metric for Network-on-Chip as well as chip multi processors. ...
... Without any need for repetition, the data can be transmitted end to end with a determinate photonic path and the basic power saving rises. In electronic NoCs, however messages are hindered, regenerated, and then transmitted to the inter router links [4,36]. So, NoCs play a vital role in the intra chip multiprocessor core interconnection while larger communication bandwidth in the NoC is needed to consider the communication among processor cores with an increase in local clock frequency in CMP. ...
Network-on-Chip (NoC) is one of the basic chip designs with advantages and challenges especially when the number of transistors increases and the data transfer rate across network is important. For these reasons, Photonic Network-on-Chip was proposed. These networks are important for intra chip communication. The data transfer with photonics between devices with long distance on the chip without any transfer rate loss is one of the most important advantages of Photonic Network-on-Chip. This paper reviews basic and fundamental concepts of Network-on-Chip and Photonic Network-on-Chip to understand their key points of designs and rules for implementation.
... (a) wave-guide (b) wave-guide bending (c) wave-(a) Cross PSE, ( b) Parallel PSE[4] ...
Nowadays multi-core processors along
with various other modules like RAM, ROM, Cache, etc
are densely placed on a single chip. System on Chip (SOC)
technology makes this possible. Also super-fast, low power,
high bandwidth interconnections of networks are needed
in SoC technology. In the past few years, on-chip
processing demands have increased because of
technological advances in 5G communications, IOT, Big
data centers etc, which are not getting accomplished using
electrical on-chip interconnection networks. All these
requirements can be fulfilled with new generation
technology called Optical Networks on Chip (ONoC). In
which electrical interconnections are replaced with optical
interconnections. The ONoC performance depends on the
Optical Routers, which are the main part of ONoC.
Optical routers are one of the important and fundamental
constituent of Optical NoCs. Till date many researchers
have proposed several Optical Router designs, every
router has its own advantages, disadvantages as well as
features. In this paper, the most efficient and commonly
... In this section, we discuss the North-Last routing algorithm, which can eliminate the set of turns needed to achieve deadlock freedom while retaining some path diversity and potential for adaptivity. Moreover, it shows flexibility in the North-Last routing algorithm such that it allows six out of eight turns and only eliminates one turn from each cycle [39] and also guarantees non-blocking. Accordingly, it seems appropriate for on-chip optical networks and high-throughput optical communications. ...
Regarding the increase in the number of cores in the electronic networks-on-chip, they may not be an ideal choice in the response of needing latency, power, and reliability. However, this problem has been effectively solved by proposing photonic networks-on-chips (PNoCs). The optical routers play an indispensable role in the PNoCs. So far, multiple routers for different architectures of PNoC have been proposed. The most of optical routers are based on Micro-Ring Resonators (MRRs); while Mach-Zehnder Interferometers (MZIs) are preferable for optical router design due to their high thermal tolerance and potential for large capacity. In this research, a 4×4 non-blocking optical router based on Mach-Zehnder Interferometer is proposed. The router is designed for a deadlock-free North-Last turning model, called NLR-OP. The NLR-OP non-blocking optical router is extended to improve network performance and physical-layer parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Moreover, assigning 30 dB to the optical power budget for interconnection using the NLR-OP router allows the Non-Blocking Torus to expand to 196 nodes. Compared to previously reported router designs, this router design allows quantifying the improvement in system performance parameters in terms of insertion loss for well-known photonic interconnection topologies. For instance, applying the NLR-OP optical router in the Non-Blocking Torus topology leads to a 38% reduction insertion loss in comparison to the previously highest performing optical router design. The routing performance of this router is simulated by the successful transmission of a 20-Gbps optical signal at the wavelength range of 1548 nm to 1557 nm for each qualified port from a choice of 10 possible physical links.
... (a) Waveguide (b) Waveguide bending (c) waveguide crossing [(a) Cross PSE, ( b) Parallel PSE[3] ...
Now days multi-core processors along with various other modules like RAM, ROM,Cache etc are densely placed on a single chip. System on Chip(SOC) technology makes this possible. Alsosuper-fast, low power, high bandwidth interconnections of networks are needed in SoC technology. All theserequirements can be fulfilled with new generation technology called Optical Networks on Chip (ONoC). TheONoC performance is mainly depends on the Optical Routers. The optical Router is the main part of ONoC.Till date many researchers has been proposed several Optical Router designs, every router has its own advantages disadvantages and features. In this paper most popular optical routers are discussed and compared
... An optical router may include the following PSEs: 1*2 cross PSE, and 1*2 parallel PSE, as shown in Fig. 4a, b, respectively [10]. [11] All PSEs have two states: the on-state when the optical signal wavelength is identical to the wavelength of the micro-ring resonance, and the off-state when the wavelength of the signal is different than the resonance wavelength. When the micro-ring is in the on-state, the optical signal changes its passing mode and this is called the drop mode; otherwise, the optical signal continues on its path, which is called the through mode. ...
... When the micro-ring is in the on-state, the optical signal changes its passing mode and this is called the drop mode; otherwise, the optical signal continues on its path, which is called the through mode. Various PSEs and different states of optical passing in these elements are shown in Fig. 4 [11]. The resonance wavelength can be determined by the materials and structure of the micro-rings. ...
Photonic network-on-chip is utilized as a candidate paradigm for important attributes such as high bandwidth and low energy consumption. In this paper, a non-blocking five-port photonic router is proposed for the 2-D mesh topology, which is called Surix. Surix has been designed for improving the physical layer and the network’s performance parameters in multi-core network topologies. Moreover, a new routing algorithm on Surix is proposed, in which turning models and the circuit switching method are used for mitigating photonic insertion loss and power consumption of the photonic layer. The proposed algorithm can select various source and destination nodes through the selected routes with the lowest insertion loss and power consumption. The simulation results show that Surix outperforms conventional routers in network performance parameters. For instance, the insertion loss of Surix in the mesh topology shows a 9.92–37.15 percent improvement compared to conventional routers.
... Hence, it is of great significance to study the power loss and crosstalk noise of ONoCs for information transmission. Nowadays, researchers mainly reduce the power loss and crosstalk noise in ONoCs by constructing new optical network topologies [7][8][9][10][11], designing optical routers [12][13][14][15][16], and using the routing algorithms [17][18][19][20]. ...
Optical networks-on-chips (ONoCs) is an effective and extensible on-chip communication technology, which has the characteristics of high bandwidth, low consumption, and low delay. In the design process of ONoCs, power loss is an important factor for limiting the scalability of ONoCs. Additionally, the optical signal-to-noise ratio (OSNR) is an index to measure the quality of ONoCs. Nowadays, the routing algorithm commonly used in ONoCs is the dimension-order routing algorithm, but the routing paths selected by the algorithm have high power loss and crosstalk noise. In this paper, we propose a 5×5 all-pass optical router model for two-dimensional (2-D) mesh-based ONoCs. Based on the general optical router model and the calculation models of power loss and crosstalk noise, a novel algorithm is proposed in ordder to select the routing paths with the minimum power loss. At the same time, it can ensure that the routing paths have the approximately optimal OSNR. Finally, we employ the Cygnus optical router to verify the proposed routing algorithm. The results show that the algorithm can effectively reduce the power loss and improve the OSNR in the case of network sizes of 5×5 and 6×6. With the increase of the optical network scale, the algorithm can perform better in reducing the power loss and raising the OSNR.
... Various optical router architectures based on 1 9 2, 2 9 1, and 2 9 2 switching element configurations are proposed in the literature [13][14][15][16][17][18][19][20][21]. Depending on the incoming request, control unit uses the routing table and passes the packets by turning the ring resonators ON or OFF. ...
... A routing algorithm based on the turning models and circuit-switching [17] reduces optical loss in the nonblocking five-port router with the two-dimensional mesh topology. For performance analysis, best-case, averagecase, and worst-case path loss are considered and the slight improvement in optical loss is reported. ...
Recently, optical network on chip (ONoC) has attracted the attention of researchers as a promising technology for low power and high bandwidth on chip communication. ONoC improves the computational efficiency of multi-core processors and chips. However, their performance suffers from power losses and limited scalability. In this paper, we present two innovative designs of five port non-blocking ONoC routers constructed by using micro-ring resonators and waveguides for low power losses and the optimum number of components. We compared the performance of the designed routers with previously reported optical routers for the power insertion loss and the requirement of micro-ring resonators. The result shows that proposed optical routers have the lowest power losses and require a lower number of micro-ring resonators. First proposed router has 1.3% lower average loss and 9.8% lower maximum port to port loss as compared to Cygnus router. The second proposed router has 4.8% lower average loss than Cygnus router. The results also show that the performance of both the routers is far better than the crossbar router. The second proposed router requires only fifteen micro-ring resonators, that is 6% lower than Cygnus router.
... Asadi et al. [22] proposed a new routing algorithm which utilizes turning models to reduce the insertion loss. They used the circuit switching method and considered Nonblocking five port crux router [23]. ...
Photonic network on chip was introduced as an efficient communication platform to overcome the existing challenges in traditional networks on chip. Optical networks provide high bandwidth and low power dissipation infrastructure. Insertion loss is one of the important parameters in photonic networks on chip. In this study, we propose a solution in routing algorithm level in order to reduce insertion loss in photonic network on chip, by passing packets through paths with lower number of optical elements. Simulation results reveal that a novel approach in the routing level decreases insertion loss as much as possible, energy consumption and optical power budget. Our proposed routing has 29.05% less insertion loss under all2all traffic pattern for blocking torus topology, and it has about 12.37% less insertion loss for TorusNX topology in comparison with primary dimension-ordered routing. Proposed routing algorithm increases both the network bandwidth and scalability.
... Two approaches have been proposed for reducing inser-tion loss in photonic networks [5]: The first approach in architecture a new topology and router (switch) for decreasing insertion loss [5][6][7][8][9]. The second approach in application level tries to decrease insertion loss by suggesting new routing [10] and mapping algorithm [11][12][13]. In this paper, the application level approach is selected (mapping) to reduce system delay and power by reducing insertion loss, wait and response time of online multi-application mapping. ...
The silicon photonic interconnection is one of the promising solutions with high bandwidth and low power consumption for overcoming electrical Network-on-Chip challenges. This communication infrastructure provides, to integrate hundreds processing cores on a chip, then this structure is suitable for running multi-application simultaneously. In this paper, a chain of algorithms have been proposed for online multi-application mapping in Photonic Network-on-Chip (PNoC). This chain contains Boundary allocation, Boundary migration and inter sub-mesh Loss Aware (LA) mapping for improving performance constrained parameter. Experimental results indicate a considerable improvement of combining the Boundary allocation and migration scheme, about 33.8% improvement in average execution time and 37.6% in energy deception.
... This will result in the advent of a vital hindrance, namely, the universal intra chip communications substructure. Here, the most important step to be taken is the challenge in future systems to realize vast bandwidths valence and correct latency needs when a vast number of processing cores [2,4]. ...
... A plethora of studies can be found focusing on intrachip global communication via packet-switched micronetworks. These present a shared medium that is pretty scalable and give ample bandwidth to substitute common busbased links [4,5]. Yet, performance-per-watt is the most vital design metric for Network-on-Chip as well as chip multi processors. ...
... Without any need for repetition, the data can be transmitted end to end with a determinate photonic path and the basic power saving rises. In electronic NoCs yet, messages are hindered, regenerated, and then transmitted to the inter router links [4,5]. So NoCs plays a vital role in the intra chip multiprocessor core interconnection while larger communication bandwidth in the NoCs is needed to consider the communication among processor cores with an increase in local clock frequency in CMP. ...
