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Conventional 6T SRAM cell. 

Conventional 6T SRAM cell. 

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Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been in...

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... cell becomes more vulnerable to noise during a read access since the "0" storage node rises to a voltage higher than ground (GND) due to a voltage divi- sion along the Pass gate transistors and inverter Pull- down devices between the pre-charged BL and the GND terminal of the cell. The ratio of the transistor width of Pull-down to Passgate, commonly referred to as the β-ratio determines how high the "0" storage node rises during a read access [4] as shown in Figure 1 for con- ventional 6T SRAM cell. Due to the scaling of the device to nanometer regime, the variation of β-ratio is signifi- cantly increased. ...
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... order to ensure robust write operation, the critical level has to be lowered than the trip point of connected inverter before the level of "0" written BL is reached to the end-point (e.g., GND). The write margin (WRM) is defined as the rest of potential difference between the BL level at which the data is flipped and the end-point (e.g., GND) as shown in Figure 1. If the cell data is flipped when the BL comes at X mV, where X mV is allowed to reach to the GND level, WRM is defined as X mV. ...
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... discharging time (TBL) depends on the BL capacitance, the cell current, and the required BL discharging level (VSEN). The amount of cell cur- rent (Icell) is determined by the strength of passgate and pull-down connected in series between the BL and GND as shown in Figure 1. The higher VT settings for pass gate, pull-down, and pull-up transistors in SRAM can suppress the sub-threshold leakage but it causes not only the reduction of Icell but also increases its variation [5]. ...
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... temperature in- creases both the SINM and WTI reduces. As shown in Figures 10 and 11 respectively. The variation has been observed at varying Vdd from 1 V to 0.6 V. ...
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... have seen the affect of Vdd and temperature on leakage power. As we know it depends exponential to Temperature and increases with temperature the same affect is seen here Figure 12. It also shows the effect of Vdd which shows that there is 7X increases in Leakage current when we increase the Vdd from 0.6 V to Vdd 1 V. ...
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... also shows the effect of Vdd which shows that there is 7X increases in Leakage current when we increase the Vdd from 0.6 V to Vdd 1 V. We have also analyzed the Leakage power with SINM as shown in Figure 13 and found that as SINM increases the Leakage power also increases which shows that with increasing Vdd the SINM increases and at the same time increasing Vdd results in increasing the leakage power [10]. ...
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... static noise margin (SNM) is the maximum amount of noise voltage VN that can be tolerated at the both inputs of the cross-coupled inverters in different directions while inverters still maintain bi-stable operating points and cell retains its data [5]. In other words, the static noise margin (SNM) quantifies the amount of noise voltage VN required at the storage nodes of SRAM to flip the cell data. The cell becomes more vulnerable to noise during a read access since the “0” storage node rises to a voltage higher than ground (GND) due to a voltage divi- sion along the Pass gate transistors and inverter Pull- down devices between the pre-charged BL and the GND terminal of the cell. The ratio of the transistor width of Pull-down to Passgate, commonly referred to as the β -ratio determines how high the “0” storage node rises during a read access [4] as shown in Figure 1 for conventional 6T SRAM cell. Due to the scaling of the device to nanometer regime, the variation of β -ratio is significantly increased. This is the primary reason for increasing SNM challenge in nanometer-scale SRAM. The ratio of inverter pull-down transistors (M1 or M2) and pull-up transistors (M3 or M4) also directly impacts the cell im- munity to noise. Weaker pull-up due to the variations makes the cell easier to flip as lowering its trip point of inverter, making the cell more vulnerable to noise. When the WL is off, the SNM becomes larger than that for read access because of no rising of “0” storage node from GND level [4]. The two kinds of SNMs for data retention and read access are referred to as “hold SNM margin” and “read SNM margin” [6]. The cell data is written by forcing the BL pair to the dif- ferential levels of “1” and “0” while WL is asserted to allow pass gate transistors (M5 or M6) connected to the BL. The potential of the corresponding storage node is pulled down to the critical level that is dependent on the ratio of transistor strengths between M5 and M3 (or M6 and M4). This ratio is referred to as γ -ratio. In order to ensure robust write operation, the critical level has to be lowered than the trip point of connected inverter before the level of “0” written BL is reached to the end-point (e.g., GND). The write margin (WRM) is defined as the rest of potential difference between the BL level at which the data is flipped and the end-point (e.g., GND) as shown in Figure 1 . If the cell data is flipped when the BL comes at X mV, where X mV is allowed to reach to the GND level, WRM is defined as X mV. As the device sizes of Pass gate and Pull-up are scaled down to nanometer regime, the variation of γ -ratio is significantly increased. That is the reason why WRM has become just as difficult as read in nanometer-scale SRAM [7]. The BL discharging time takes a large percentage of the total access time. The discharging time (TBL) depends on the BL capacitance, the cell current, and the required BL discharging level (VSEN). The amount of cell current (Icell) is determined by the strength of passgate and pull-down connected in series between the BL and GND as shown in Figure 1 . The higher VT settings for pass gate, pull-down, and pull-up transistors in SRAM can suppress the sub-threshold leakage but it causes not only the reduction of Icell but also increases its variation [5]. In this paper we have proposed a novel PP based 9T SRAM Cell Figure 2 . In this cell one extra signal RWL is used during read operation, during read operation we keep it at gnd voltage otherwise the value remains high. The true storage nodes are separated from the two virtual storage nodes connected between the stacked PMOS. If we look at the figure we will find that there is one extra NMOS transistor is used which creates a discharging path. It is connected to the RWL. The discharging path is used such that to discharge a precharged high bitline during the read operation. This circuit has certain advantages like it does not have read problem as the discharging path is isolated from the true storage nodes. The write ability is also not disturbed in this structure. We have used a single wordline for both the operations read and write .This cell has better stability and it is power efficient. In this section, we describe our cell design in Figure 2 . As mentioned previously, it is composed of two cross coupled P-P-N inverters, and data is stored in node Q and node Qb in a complementary manner. Transistors P1, PP3, and ND1 form a P-P-N inverter and P1, PP4, ND2 form another. ND1 provides the read current path for discharging a bitline (BL) or its complementary (BLB), depending on the stored values of Q and Qb, respectively. The source terminal of this transistor is connected to the VGND pin, which connects to the ground voltage only during the read operation. Anytime else, it stays high to curb un- necessary leakage current.V1 and V2 are located between the two cascaded P-MOS transistors forming the P-P-N inverter. Q and Qb are the storage nodes .BL and BLB are bitlines while Wl is the word line as in conventional 6T SRAM cell. During a write operation .initially in this PP based 9T SRAM Figure 2 , storage node Q stores “0” while Qb stores “1”. To perform a write operation, the wordline WL is enabled and one bitline, e.g., BLB, is pulled down to ground in advance. When the supply voltage is relatively high (e.g., 1 V), node Qb (storing “1”) here in this case will be pulled down directly through the discharging path formed by. In turn, node Q will be charged up to complete the data-flipping process. In general, the lower portion of our P-P-N inverter pair can be viewed as a latch consisting of PP3-ND1and PP4- ND2. In some sense, this latch takes node V1and node V2 as the pseudo supply terminals. In step 1, Qb is pulled down quickly to nearly the ground voltage at the begin- ning of the write operation since it is driven by BLB tied to strong “0”. Qb via the PMOS between them (PP3), reducing the voltage of Qb to a lower middle voltage. During this time period, PP3 and PP4 controlled by Qb still conducts weakly to pull up voltage at node Q, Due to the coupling effect of parasitic capacitances the voltage of Qb, which is in the floating state, rises with node Q but only slightly. In step 2, the data flipping finally takes place when Q is strong enough to conduct the PDR transistor to discharge Qb down to the ground voltage. It is worth mentioning that even though such a write mechanism takes relatively longer time to accomplish the data flipping, it is still shorter than the read access time, and therefore, overall it does not introduce any operating frequency penalty. We can also further improve the cell’s write-ability by strengthening the access transistors (NA1 and NA2). It does not affect the read performance. To perform a read operation, the wordline WL is enabled and RWL is pulled down to ground to allow bitline discharging. Assuming that the data stored at Q is now “0”. Since data node Q and Qb are isolated from bitline BL by PP2 and PP3 (which is between the true storage node Q) and thus the so-called read current (which is the current used to discharge a bitline) does not flow through the storage node Qb but through the bypassing ND 3 as indicated in Figure 2 . This is the main reason why the read stability does not degrade at all in our cell. As for a 6T cell, the read current flows through ...
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... static noise margin (SNM) is the maximum amount of noise voltage VN that can be tolerated at the both inputs of the cross-coupled inverters in different directions while inverters still maintain bi-stable operating points and cell retains its data [5]. In other words, the static noise margin (SNM) quantifies the amount of noise voltage VN required at the storage nodes of SRAM to flip the cell data. The cell becomes more vulnerable to noise during a read access since the “0” storage node rises to a voltage higher than ground (GND) due to a voltage divi- sion along the Pass gate transistors and inverter Pull- down devices between the pre-charged BL and the GND terminal of the cell. The ratio of the transistor width of Pull-down to Passgate, commonly referred to as the β -ratio determines how high the “0” storage node rises during a read access [4] as shown in Figure 1 for conventional 6T SRAM cell. Due to the scaling of the device to nanometer regime, the variation of β -ratio is significantly increased. This is the primary reason for increasing SNM challenge in nanometer-scale SRAM. The ratio of inverter pull-down transistors (M1 or M2) and pull-up transistors (M3 or M4) also directly impacts the cell im- munity to noise. Weaker pull-up due to the variations makes the cell easier to flip as lowering its trip point of inverter, making the cell more vulnerable to noise. When the WL is off, the SNM becomes larger than that for read access because of no rising of “0” storage node from GND level [4]. The two kinds of SNMs for data retention and read access are referred to as “hold SNM margin” and “read SNM margin” [6]. The cell data is written by forcing the BL pair to the dif- ferential levels of “1” and “0” while WL is asserted to allow pass gate transistors (M5 or M6) connected to the BL. The potential of the corresponding storage node is pulled down to the critical level that is dependent on the ratio of transistor strengths between M5 and M3 (or M6 and M4). This ratio is referred to as γ -ratio. In order to ensure robust write operation, the critical level has to be lowered than the trip point of connected inverter before the level of “0” written BL is reached to the end-point (e.g., GND). The write margin (WRM) is defined as the rest of potential difference between the BL level at which the data is flipped and the end-point (e.g., GND) as shown in Figure 1 . If the cell data is flipped when the BL comes at X mV, where X mV is allowed to reach to the GND level, WRM is defined as X mV. As the device sizes of Pass gate and Pull-up are scaled down to nanometer regime, the variation of γ -ratio is significantly increased. That is the reason why WRM has become just as difficult as read in nanometer-scale SRAM [7]. The BL discharging time takes a large percentage of the total access time. The discharging time (TBL) depends on the BL capacitance, the cell current, and the required BL discharging level (VSEN). The amount of cell current (Icell) is determined by the strength of passgate and pull-down connected in series between the BL and GND as shown in Figure 1 . The higher VT settings for pass gate, pull-down, and pull-up transistors in SRAM can suppress the sub-threshold leakage but it causes not only the reduction of Icell but also increases its variation [5]. In this paper we have proposed a novel PP based 9T SRAM Cell Figure 2 . In this cell one extra signal RWL is used during read operation, during read operation we keep it at gnd voltage otherwise the value remains high. The true storage nodes are separated from the two virtual storage nodes connected between the stacked PMOS. If we look at the figure we will find that there is one extra NMOS transistor is used which creates a discharging path. It is connected to the RWL. The discharging path is used such that to discharge a precharged high bitline during the read operation. This circuit has certain advantages like it does not have read problem as the discharging path is isolated from the true storage nodes. The write ability is also not disturbed in this structure. We have used a single wordline for both the operations read and write .This cell has better stability and it is power efficient. In this section, we describe our cell design in Figure 2 . As mentioned previously, it is composed of two cross coupled P-P-N inverters, and data is stored in node Q and node Qb in a complementary manner. Transistors P1, PP3, and ND1 form a P-P-N inverter and P1, PP4, ND2 form another. ND1 provides the read current path for discharging a bitline (BL) or its complementary (BLB), depending on the stored values of Q and Qb, respectively. The source terminal of this transistor is connected to the VGND pin, which connects to the ground voltage only during the read operation. Anytime else, it stays high to curb un- necessary leakage current.V1 and V2 are located between the two cascaded P-MOS transistors forming the P-P-N inverter. Q and Qb are the storage nodes .BL and BLB are bitlines while Wl is the word line as in conventional 6T SRAM cell. During a write operation .initially in this PP based 9T SRAM Figure 2 , storage node Q stores “0” while Qb stores “1”. To perform a write operation, the wordline WL is enabled and one bitline, e.g., BLB, is pulled down to ground in advance. When the supply voltage is relatively high (e.g., 1 V), node Qb (storing “1”) here in this case will be pulled down directly through the discharging path formed by. In turn, node Q will be charged up to complete the data-flipping process. In general, the lower portion of our P-P-N inverter pair can be viewed as a latch consisting of PP3-ND1and PP4- ND2. In some sense, this latch takes node V1and node V2 as the pseudo supply terminals. In step 1, Qb is pulled down quickly to nearly the ground voltage at the begin- ning of the write operation since it is driven by BLB tied to strong “0”. Qb via the PMOS between them (PP3), reducing the voltage of Qb to a lower middle voltage. During this time period, PP3 and PP4 controlled by Qb still conducts weakly to pull up voltage at node Q, Due to the coupling effect of parasitic capacitances the voltage of Qb, which is in the floating state, rises with node Q but only slightly. In step 2, the data flipping finally takes place when Q is strong enough to conduct the PDR transistor to discharge Qb down to the ground voltage. It is worth mentioning that even though such a write mechanism takes relatively longer time to accomplish the data flipping, it is still shorter than the read access time, and therefore, overall it does not introduce any operating frequency penalty. We can also further improve the cell’s write-ability by strengthening the access transistors (NA1 and NA2). It does not affect the read performance. To perform a read operation, the wordline WL is enabled and RWL is pulled down to ground to allow bitline discharging. Assuming that the data stored at Q is now “0”. Since data node Q and Qb are isolated from bitline BL by PP2 and PP3 (which is between the true storage node Q) and thus the so-called read current (which is the current used to discharge a bitline) does not flow through the storage node Qb but through the bypassing ND 3 as indicated in Figure 2 . This is the main reason why the read stability does not degrade at all in our cell. As for a 6T cell, the read current flows through the storage node directly, thereby causing read disturbance , i.e. , the voltage at data node Q will rise temporarily. This will degrade the read stability because the cell flipping will be more likely to take place. The pull-up transistors P1 and P2 are usually made weaker for easy write operation just like in a conventional 6T cell. While the pull-down transistors ND1 and ND2, forming the cell discharging paths, need to be stronger to facilitate a larger read current and thereby a quicker access. The pass gate transistors NA1 and NA2 need to be strong enough to serve as high-conduction paths between the accessed cell and the bitlines during both the read and write operations. The two pull-up ...
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... static noise margin (SNM) is the maximum amount of noise voltage VN that can be tolerated at the both inputs of the cross-coupled inverters in different directions while inverters still maintain bi-stable operating points and cell retains its data [5]. In other words, the static noise margin (SNM) quantifies the amount of noise voltage VN required at the storage nodes of SRAM to flip the cell data. The cell becomes more vulnerable to noise during a read access since the “0” storage node rises to a voltage higher than ground (GND) due to a voltage divi- sion along the Pass gate transistors and inverter Pull- down devices between the pre-charged BL and the GND terminal of the cell. The ratio of the transistor width of Pull-down to Passgate, commonly referred to as the β -ratio determines how high the “0” storage node rises during a read access [4] as shown in Figure 1 for conventional 6T SRAM cell. Due to the scaling of the device to nanometer regime, the variation of β -ratio is significantly increased. This is the primary reason for increasing SNM challenge in nanometer-scale SRAM. The ratio of inverter pull-down transistors (M1 or M2) and pull-up transistors (M3 or M4) also directly impacts the cell im- munity to noise. Weaker pull-up due to the variations makes the cell easier to flip as lowering its trip point of inverter, making the cell more vulnerable to noise. When the WL is off, the SNM becomes larger than that for read access because of no rising of “0” storage node from GND level [4]. The two kinds of SNMs for data retention and read access are referred to as “hold SNM margin” and “read SNM margin” [6]. The cell data is written by forcing the BL pair to the dif- ferential levels of “1” and “0” while WL is asserted to allow pass gate transistors (M5 or M6) connected to the BL. The potential of the corresponding storage node is pulled down to the critical level that is dependent on the ratio of transistor strengths between M5 and M3 (or M6 and M4). This ratio is referred to as γ -ratio. In order to ensure robust write operation, the critical level has to be lowered than the trip point of connected inverter before the level of “0” written BL is reached to the end-point (e.g., GND). The write margin (WRM) is defined as the rest of potential difference between the BL level at which the data is flipped and the end-point (e.g., GND) as shown in Figure 1 . If the cell data is flipped when the BL comes at X mV, where X mV is allowed to reach to the GND level, WRM is defined as X mV. As the device sizes of Pass gate and Pull-up are scaled down to nanometer regime, the variation of γ -ratio is significantly increased. That is the reason why WRM has become just as difficult as read in nanometer-scale SRAM [7]. The BL discharging time takes a large percentage of the total access time. The discharging time (TBL) depends on the BL capacitance, the cell current, and the required BL discharging level (VSEN). The amount of cell current (Icell) is determined by the strength of passgate and pull-down connected in series between the BL and GND as shown in Figure 1 . The higher VT settings for pass gate, pull-down, and pull-up transistors in SRAM can suppress the sub-threshold leakage but it causes not only the reduction of Icell but also increases its variation [5]. In this paper we have proposed a novel PP based 9T SRAM Cell Figure 2 . In this cell one extra signal RWL is used during read operation, during read operation we keep it at gnd voltage otherwise the value remains high. The true storage nodes are separated from the two virtual storage nodes connected between the stacked PMOS. If we look at the figure we will find that there is one extra NMOS transistor is used which creates a discharging path. It is connected to the RWL. The discharging path is used such that to discharge a precharged high bitline during the read operation. This circuit has certain advantages like it does not have read problem as the discharging path is isolated from the true storage nodes. The write ability is also not disturbed in this structure. We have used a single wordline for both the operations read and write .This cell has better stability and it is power efficient. In this section, we describe our cell design in Figure 2 . As mentioned previously, it is composed of two cross coupled P-P-N inverters, and data is stored in node Q and node Qb in a complementary manner. Transistors P1, PP3, and ND1 form a P-P-N inverter and P1, PP4, ND2 form another. ND1 provides the read current path for discharging a bitline (BL) or its complementary (BLB), depending on the stored values of Q and Qb, respectively. The source terminal of this transistor is connected to the VGND pin, which connects to the ground voltage only during the read operation. Anytime else, it stays high to curb un- necessary leakage current.V1 and V2 are located between the two cascaded P-MOS transistors forming the P-P-N inverter. Q and Qb are the storage nodes .BL and BLB are bitlines while Wl is the word line as in conventional 6T SRAM cell. During a write operation .initially in this PP based 9T SRAM Figure 2 , storage node Q stores “0” while Qb stores “1”. To perform a write operation, the wordline WL is enabled and one bitline, e.g., BLB, is pulled down to ground in advance. When the supply voltage is relatively high (e.g., 1 V), node Qb (storing “1”) here in this case will be pulled down directly through the discharging path formed by. In turn, node Q will be charged up to complete the data-flipping process. In general, the lower portion of our P-P-N inverter pair can be viewed as a latch consisting of PP3-ND1and PP4- ND2. In some sense, this latch takes node V1and node V2 as the pseudo supply terminals. In step 1, Qb is pulled down quickly to nearly the ground voltage at the begin- ning of the write operation since ...

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