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The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated thro...
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... transfer to PMOS bulk load through A node is V a ¼ 1:12 V and V dd , voltage transfer to NMOS bulk driver through B node which is V b ¼ À0:12 V and V ss , voltage transfer to NMOS bulk access through C node is V c ¼ 0:8 V and À0.12 V. With this stimulus in the control circuit, the body bias control signals for standby and active mode are shown in Fig. ...
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Citations
... One of the suggested solutions to the power dissipation problem is to scale back the power supply, but the reliability of the SRAM cell poses another challenge in this. Besides this, issues like data stability, delay and high sensitivity to process variation [7][8][9][10][11][12] also contributes to overall performance of SRAM. and two PMOS (PM 3 and PM 4 ) transistors. ...
The typical memory for very large scale integrated (VLSI) circuits has traditionally been static random access memory (SRAM). This is so because SRAM is a speedier technology than the ones that were previously mentioned. SRAM, however, has a high power consumption rate. Due to its importance in the memory architecture, it is crucial to lower the power consumption of SRAM cells. This literature review's major goal is to provide innovative and effective strategies for creating low power SRAM cells. This study provides several circuit topologies and methodologies to compute stability, leakage current, delay, and power, as well as novel techniques for designing SRAM cells based on eight transistors (8T). The static random access memory (SRAM) is frequently chosen over dynamic random access memory (DRAM) due to faster speed and lower power consumption. It is named static since no modification or action, i.e. refreshing, is required to maintain the data intact. The leakage current in SRAM, however, frequently rises and impairs its performance when technology nodes are scaled down. Voltage scaling, which also impacts the stability and latency of SRAM, is chosen as a solution to this problem. In this study, a separate (isolated) read port is employed to increase read stability while a negative bit-line (NBL) write aid circuit is used to improve write capability. In terms of write static noise margin (WSNM), write latency, read static noise margin (RSNM), and other metrics, the suggested design has been compared to state-of-the-art work. The following is how the paper is divided into sections: 1. Introduction. Section 2 describes related work. The suggested work is in section 3. Results and discussion are included in section 4 and section 5 Conclusions.
... The leakage power comparison graph is shown in Fig. 14. It is calculated by deactivating the lines which means calculating the power during hold/standby operation [13] [14]. As compared to the other cells the leakage power is lower for the proposed. ...
Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9T SRAM cell with independent read/write operation and compares its performance with 6T, 8T, and 10T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.
