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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of p...
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... planar transistors are still very commonly used for chips at less advanced nodes (>20 nm) [14]. As depicted in Figure 1, chip design and manufacturing costs increase exponentially as technology nodes advance and when changing from transistors with a planar architecture to those with a non-planar architecture. In a rough comparison, Figure 1 shows that the chip design cost for a planar region is around USD 1.6 million per node, whereas for a non-planar region it is about USD 40 million per node (nm) [15]. ...
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... depicted in Figure 1, chip design and manufacturing costs increase exponentially as technology nodes advance and when changing from transistors with a planar architecture to those with a non-planar architecture. In a rough comparison, Figure 1 shows that the chip design cost for a planar region is around USD 1.6 million per node, whereas for a non-planar region it is about USD 40 million per node (nm) [15]. It is not surprising that only 8.5% of global fabrication capacity is able to be used to fabricate advanced AI chips at ≤16 nm. ...
Citations
... Numerous studies have successfully applied the Taguchi-based GRA method to optimize semiconductor devices through numerical simulations. For instance, Mah et al [27] utilized this method to optimize device parameters, validating their simulation results against experimental data, which confirmed the accuracy of their models. Similarly, Rezali et al [28] optimized doping levels and work function tuning, correlating simulation outcomes with experimental measurements to effectively predict device behavior under various conditions. ...
The intriguing behavior of doped polyanilinine/graphene oxide (PANI/GO) offers a solution to the pivotal problem of device stability against moisture in perovskite solar cell (PSC). Tunable bandgap formation of doped PANI/GO with an absorber layer allows effective flexibility for charge carrier conduction and reduced series resistance further boosting the cell performance. Herein, the L9 Orthogonal Array (OA) Taguchi-based grey relational analysis (GRA) optimization was introduced to intensify the key output responses. Furthermore, this work also delved into incorporating a Pb-free absorber perovskite layer, formamidinium tin triiodide (FASnI3), and concomitantly eluding the environmentally hazardous substance. The numerical optimization supported by statistical analysis is based on experimental data to attain the utmost peak cell efficiency. Taguchi’s L9 OA-based GRA predictive modeling recorded over one-fold enhancement over experimental results, reaching as high as 20.28% power conversion efficiency (PCE). Despite that, the PCE of the structures is severely affected by interface defects at the electron transport layer/absorber (ETL/Abs) vicinity, which is almost zero at merely 1 × 10¹⁴ cm⁻², manifesting that control measures need to be taken into account. This work deduces the feasibility of ETL/Abs stack structure in replacing the conventional Pb-based perovskite absorber layer, while maximizing the potential use of doped PANI/GO as a hole transport layer (HTL).
... [20] To mitigate short-channel effects in FinFETs, thinning the fins is crucial, but this presents fabrication challenges. [21][22] To address this, the -FinFET structure is proposed, offering several advantages over conventional FinFET designs. Firstly, the substantial silicon base provided by the inverted T-shaped gate prevents the fins from sliding off during processing, enhancing device reliability. ...
... The process of scaling Metal Oxide Semiconductor Field Effect Transistors (MOSFET) has yielded a substantial increase in device density per wafer, consequently resulting in a remarkable reduction in the cost per chip [1]. The transition from the era of microelectronics to the emerging era of nanoelectronics will not only facilitate the widespread integration of electronic components, enabling their miniaturization and cost reduction to the extent that they can be incorporated into virtually any object, including dissolvable and wearable products [2], [3]. The downsizing of transistors, resulting from device scaling, also brings forth additional advantages. ...
... The assessment of mobility serves as a pivotal parameter in the evaluation of a HK dielectric as a viable substitute for SiO2 [15], [16]. The aforementioned approach holds significant influence over various transistor metrics, including but not limited to saturation drain current (Id(sat)), switching speed, threshold voltage (Vth), transconductance (gm), Drain Induced Barrier Lowering (DIBL), and subthreshold swing (SS) [3]. The employment of FinFET technology with HK-MG offers a number of advantages, the most significant of which is the reduction of the subthreshold swing, which is accomplished while simultaneously keeping the DIBL impact at a low level [17], [18]. ...
... In contrast to silicon (Si), SiO2 exhibits a thermal conductivity that is diminished by two orders of magnitude, thereby compromising the operational efficiency of the device. The phenomenon referred to is commonly known as the self-heating effect [3], [21]. ...
The progress in semiconductor technology has played a crucial role in enhancing human existence by introducing significant innovations. The pursuit of high-performance devices utilizing novel materials has emerged as a crucial avenue for surmounting the existing limitations of silicon-based technologies. This paper presents an evaluation of the diverse short channel effects (SCEs) exhibited by the double gate n-FinFET structure, considering the influence of temperature on channel materials using metal gate (MG) as Gallium Arsenide (GaAs) alongside High-K dielectric oxide materials such as Hafnium Oxide (HfO2), Lanthanum Oxide (La2O3) and Lanthanum Aluminum Oxide (LaAlO3) in comparison with traditional Silicon Dioxide (SiO2). The investigation and presentation of the impact of gate length (Lg), channel width (Wch), doping, and varying Temperature (275k-450k) on several short channel effects (SCEs), namely Drain Induced Barrier Lowering (DIBL), Subthreshold Slope (SS), threshold voltage (Vth) roll-off, Transconductance (gm) and ON-OFF current ratio (ION / IOFF) have been thoroughly examined using the aforementioned materials. The utilization of FinFET technology using HK-MG presents notable benefits in terms of mitigating the subthreshold swing while concurrently maintaining a low drain-induced barrier lowering (DIBL) effect.
... Currently, the basic element of digital integrated electronics, acting as a normally open switch, is a silicon field-effect transistor with an induced channel [1]. In order to fulfill the three main requirements for such switching elements to further increase the degree of integration of the element base of micro-and nanoelectronics, in particular, reducing geometric dimensions, increasing switching speed, and reducing power dissipation, developers of this kind of device structures have been forced to reduce the operating voltages at the gate and drain of the transistor [2,3], choose alternative materials for its conducting channel [4][5][6], use other principles for controlling its switching [7,8], and also look for new design and topological solutions [3][4][5][6][7][8][9][10][11][12][13][14][15][16]. At least most of these requirements can be satisfied by a vertical ballistic nanotransistor with a cylindrical gate [3,[12][13][14][15][16] under the following conditions: (1) in a cylindrical conducting channel, there is a onedimensional electron gas under the conditions of the electric quantum limit [17]; (2) the conducting channel is formed from a very high-tech material with very high electron mobility [18]; (3) the material of the transistor's insulating matrix is technologically compatible with the materials of its conductive channel and electrodes; (4) as in a tunnel field-effect transistor [7,8,16], the height and width of the potential barrier for electrons is directly controlled by the gate voltage [16]; and (5) in the open state, the electrical conductivity of the transistor channel tends to the maximum possible quantum mechanical value [19], where e is the elementary charge and ħ is the reduced Planck constant. ...
A design and topological solution for a tunnel field-effect transistor of a new type is proposed and
the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a
cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3
matrix. For the given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor
composition varying along the transistor channel is found, at which, unlike a conventional tunnel
field-effect transistor, not only is the complete suppression of the quantum barrier for electrons by a positive
gate voltage ensured but also the minimum possible electrical resistance of the transistor channel is achieved.
The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-
mechanical description of the electron transport in its channel, taking into account the nonparabolic
nature of the band structure of the semiconductor.
... 1. ВВЕДЕНИЕ В настоящее время базовым элементом цифровой интегральной электроники, выполняющим роль нормально-разомкнутого ключа, является кремниевый полевой МДП-транзистор с индуцированным каналом [1]. Выполнение предъявляемых к такого рода ключевым элементам трех основных требований для дальнейшего увеличения степени интеграции элементной базы микро-и наноэлектроники, в частности, уменьшения геометрических размеров, увеличения скорости переключения и снижения рассеиваемой мощности, вынуждает разработчиков такого рода приборных структур уменьшать значения рабочих напряжений на затворе и стоке транзистора [2,3], выбирать альтернативные материалы для его проводящего канала [4][5][6], использовать иные принципы управления его переключением [7,8], а также искать новые конструктивно-топологические решения [3][4][5][6][7][8][9][10][11][12][13][14][15][16]. По крайней мере, большую часть вышеперечисленных требований может удовлетворить вертикальный баллистический нанотранзистор с цилиндрическим затвором [3,[12][13][14][15][16], у которого: 1) в цилиндрическом проводящем канале находится одномерный электронный газ в условиях электрического квантового предела [17]; 2) проводящий канал сформирован из весьма высокотехнологичного материала с очень высокой подвижностью электронов [18]; 3) материал изоляционной матрицы транзистора технологически совместим с материалами его проводящего канала и электродов; 4) как и в туннельном полевом транзисторе [7,8,16] высота и ширина потенциального барьера для электронов непосредственно управляется затворным напряжением [16]; 5) в открытом состоянии электрическая проводимость канала транзистора стремится к максимально возможному квантово-механическому значению [19], где e -элементарный заряд, ħ -редуцированная постоянная Планка. ...
A design-topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3 matrix. For a given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only the complete suppression of the quantum barrier for electrons by a positive gate voltage is ensured, but also the minimum possible electrical resistance of the transistor channel. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the non-parabolic nature of the band structure of the semiconductor.
... Also, the short channel characteristics can be controlled to a large extent as both horizontal and vertical channel regions use thin body regions. Further, the use of different gate dielectrics as a stack helps to achieve an improved performance of the device due to the alteration in the gate capacitance of the device [23] To enhance the carrier's mobility in the device, high speed operation and achieve higher transconductance, a concept of heterojunction could be implemented [24]. ...
... In order to meet performance requirements and address the limitations of planar bulk transistors when scaling down to sizes below 22 nm, the semiconductor industry has developed new technologies such as the fin field-effect transistor (FinFET) [10]. The FinFET is considered the most promising candidate for replacing traditional planar bulk devices beyond the 22 nm technology node, owing to their excellent performance in reducing leakage current and improving short channel behavior [11,12]. ...
In this study, we developed a facilitated ferroelectric high-k/metal-gate n-type FinFET based on Hf0.5Zr0.5O2. We investigated the impact of the hysteresis effect on device characteristics of various fin-widths and the degradation induced by stress on the ferroelectric FinFET (Fe-FinFET). We clarified the electrical characteristics of the device and conducted related reliability inspections. For the Fe-FinFET, the hysteresis behavior of the Hf0.5Zr0.5O2-based gate stack in the Si-fin body is apparent, especially at narrower fin-widths, which affects device performance and reliability under voltage stress. The gate ferroelectric film is worsened after voltage stress with higher impact ionization, resulting in hysteresis degradation and serious induced device performance degradation. It is suggested that the hysteresis degradation is caused by both a shift in polarization of the gate ferroelectric film and generation of interface traps after high-energy carrier stress, which was confirmed by crystal structure inspection.
... Fig. 4(a) & 4(b) and Fig. 5 illustrate the I on , I off , and I on /I off ratio characteristics for a DG n-FinFET with various gate dielectric constants [17]. The greatest results are obtained when ZrO 2 is employed as the gate dielectric layer [18]. The I on of SiGe channel material is greater than that of 3C-SiC channel material, which is important for system efficiency. ...
The scalability of bulk CMOS faced various possible issues due to inherent material and process innovation constraints. Alternatively, transistor devices with supplementary gates, such as the Fin Field-effect transistor (FinFET) structure has attracted developing interest during the last few generations of their emergence, attributable to the appropriate control of the gate electrode over subthreshold parameters and seem to be favorable for Ultra large-scale integration, resulting in excessive immune function to short-channel effects (SCEs). In this paper, we will see the effect of several types of high-k gate dielectrics materials i.e Hafnium oxide (HfO2), Lanthanum doped zirconium oxide (LaZrO2), Silicon dioxide (SiO2), crystalline-silicon (c-Si), and polycrystalline-silicon (poly-Si), etc. channels are characterized for the short channel effects (SCEs), leakage current, Ion/Ioff ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS). The effect of important device parameters is considered regarding SCEs. The variation of the materials indicates improvements for the SCEs in FinFETs device architecture and also enhanced effective carrier mobility. Hence, we can clearly see that the use of high-k gate material has allowed for effective control of the diminishing of short channel effects.
... The study of the variation of the process parameters and interaction effects delivered the optimized values of the process parameters to attain the desired output. The results found through the SILVACO simulations were in good agreement with the nominal values of the PMOS device as anticipated by the International Technology Roadmap for Semiconductors (ITRS) [30]. ...
In this paper, the design steps of an n-MOSFET have been described and then the electrical characterization of this MOSFET is simulated at 100 nm by using the SILVACO ATLAS software, which is a process and device simulation software tool. The MOS device is virtually fabricated using ATHENA in SILVACO and simulations have been performed with help of ATLAS software, and all graphs are plotted using TONYPLOT in the SILVACO. The simulated results are then analyzed to study the n-MOSFET device's mesh structure, transfer and output characteristics of the same, doping and carrier concentration plot, etc. From the simulation study, we found that the designed device is working well for various bias conditions.
... The study of the variation of the process parameters and interaction effects delivered the optimized values of the process parameters to attain the desired output. The results found through the SILVACO simulations were in good agreement with the nominal values of the PMOS device as anticipated by the International Technology Roadmap for Semiconductors (ITRS) [30]. ...
In this era of industrialization, environmental pollution is one of the major problems of the entire globe. Different technologies are being employed for the removal of the pollutants from both terrestrial and aquatic environments. The most commonly used technologies for environmental remediation include; filtration, adsorption, chemical reactions, photocatalysis, etc. Currently, the application of nanotechnology-based materials for environmental remediation has attained extraordinary popularity due to their unique mechanical properties, higher surface area, chemical reactivity, regeneration efficiency, and cost-effectiveness. Such nanomaterials are applied for the removal of different environmental (organic or inorganic) pollutants such as dyes (anionic and cationic) from industrial sources, heavy metals in different forms, gaseous toxic compounds, etc. These nanomaterials can be categorized on the basis of their production sources (inorganic, organic, carbon-based, etc.). Presently it is a challenge to produce eco-friendly, and nontoxic nanomaterials, which can be easily disposed of after treatment of air, water, or soil. Thus, this chapter is based on the fabrication of nanomaterials from different sources and their application for sustainable environmental remediation. Further, the nanotechnology-based techniques being applied in environmental remediation will be discussed with their present advancements and future aspects.
