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![Chip Design and Manufacturing Cost under Different Process Nodes: Data Source from IBS [2].](publication/340843129/figure/fig1/AS:883120060506112@1587563638610/Chip-Design-and-Manufacturing-Cost-under-Different-Process-Nodes-Data-Source-from-IBS.png)
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As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramaticall...
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... to the survey from the International Business Strategy Corporation (IBS), the increase of design cost for each generation technology has exceeded 50% after 22 nm process, including EDA, design verification, IP core, tape-out, and so forth. For instance, the total design cost of 7 nm process is about 300 million dollars, and that of 3 nm process is expected to increase 5 times up to 1.5 billion dollars [2], as depicted in Figure 1. Thus, the difficulties for implementing a high-performance chip upgrade based on process improvement are increasing and the price-performance ratio is increasing. ...
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Recently, the issue of malicious circuit alteration and attack draws more attention than ever before due to the globalization of IC design and manufacturing. Malicious circuits, also known as hardware Trojans, are found able to degrade the circuit performance or even leak confidential information, and accordingly it is definitely an issue of immedi...
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... Each chiplet perform can be a specific function or can be a component like CPU, GPU, I/O controller, memory etc. They offer several benefits [16,17]. The most important benefits being modularity where they are able to mix and match individual components to best suit the application. ...
Semiconductors play a very important role in modern society. The improvement in performance of semiconductors is what has enabled the world to grow at such a fast pace. For decades scaling has been done through Moore’s law i.e performance improvements have been obtained due to transistor scaling where the number of transistors per unit area increase is what has contributed to the increase in performance. However, with transistor scaling reaching its limitations we need to find alternate methods to enhance silicon design to suit the computational need of modern society. To address this problem we will be looking into a few methods that enable performance scaling with a focus on analysing the most popular implementation of each in the industry.
... This integration presents an opportunity for higher performance through improved memory access speeds. For example, 3D packaging technology enables the stacking of CPU and memory dies, leading to enhanced memory bandwidth and reduced transmission latency thanks to shorter interconnects between the dies [15]. Ongoing research is focused on improving the communication quality and interconnect in interposers. ...
... The necessity of integrating multiple dies or chiplets within a single package draws significant attention to the development of advanced packaging technologies, placing semiconductor engineers and physicists at the forefront of their capabilities. Accommodating an increased number of silicon dies within a reduced footprint necessitates both vertical and horizontal stacking, involving additional wire bonding, densely packed smaller bumps, heightened routing complexity, and potential interference from neighboring signal paths [16] [15]. Various packaging technologies have emerged to address these wide design challenges for advancing HI. ...
The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.
... 3D System-in-package (SiP) solutions are a form of improving chip density by stacking silicon dies in three-dimensional space while connecting these chips to each other. 3D integration refers to the ability to connect dies even when vertically stacked, through the use of Through Si Via (TSV) technology [16]. 3D SiP packaging involves optimizing the use of 3D integration by packaging these dies into chips through intelligent positioning, such as Package-on-Package designs that layer larger packages (such as logic dies) over smaller memory dies. ...
... 3D SiP Packaging and Integration thus improves on the effectiveness of circuits and transistor density in a way that goes beyond Moore's law. Instead of relying purely on transistor density, SiP technologies, and especially 3D SiP, go beyond Moore's law in a way that has been called "More than Moore" [16]. This is because the density of 3D SiP is not gained through any one circuit's density, but rather the density of the entire circuit through its 3D packaging and interconnection. ...
... While much has been said about the potential thermal or mechanical limits of transistor density in integrated circuits, the intent of Moore's Law may be understood to be the density of circuits, which 3D SiP does provide for. Interconnection is possible in the modern context because of the ability to use very short connecting wires with high densities [16]. ...
Moore's Law is a concept that notes the doubling of the number of transistors on a microchip around every two years, resulting in exponential advancement in computing power and diminishing costs. However, as transistor sizes have approached the physical limits of silicon-based technology, maintaining this pace of growth has become increasingly challenging. As a result, researchers have been exploring alternative solutions, such as System-in-package(SiP), Chiplets, Non-volatile memory, Biocomputing, quantum computing, and photonics. While these technologies are still in the early stages of development, they offer promising solutions to the challenges facing the continued growth of computing power. As we continue to explore new avenues for technological advancement, we may find that Moore's Law continues to hold true in unexpected and exciting ways.
... Ref. [5] explains that the semiconductor industry is a very complex industry from a supply chain perspective. Meanwhile, Ref. [6] explained that in the process of designing and manufacturing heterogeneous chips, there are complex and challenging factors related to the difficulty of combining different chips and balancing performance, power, and cost. In particular, PiM has the challenges of existing semiconductor technology and, at the same time, faces new technological challenges such as workload analysis and classification, OS and runtime support, and coherency and consistency [7]. ...
Processing-in-Memory (PiM), which combines a memory device with a Processing Unit (PU) into an integrated chip, has drawn special attention in the field of Artificial Intelligence semiconductors. Currently, in the development and commercialization of PiM’s technology, there are challenges in the hegemony competition between the PU and memory device industries. In addition, there are challenges in finding strategic partnerships rather than independent development due to the complexity of technological development caused by heterogeneous chips. In this study, patent Main Path Analysis (MPA) is used to identify the majority and complementary groups between PU and memory devices for PiM. Subsequently, Document-to-Vector (Doc2Vec) and similarity-scoring analyses are used to determine the potential partners for technical cooperation required for PiM technology development for the majority group identified. According to the empirical results, PiM core technology is evolving from PU to memory device with an ‘architecture-operation-architecture’ design pattern. The ten ASIC candidates are identified for strategic partnerships with memory device suppliers. Those partnership candidates include several mobile AP firms, implying PiM’s opportunities in the field of mobile applications. It suggests that memory device suppliers should prepare for different technology strategies for PiM technology development. This study contributes to the literature and high-tech industry via the proposed quantitative technology partnership model.
... The stress-induced failure in chiplet applications is costly and unbearable because the failure of a single die would cause failure of the monolithic chip [30], but current studies are focused on the warpage behavior investigation of multi-chiplet systems [32,37]. Accordingly, the stress generation mechanism during fabrication of chiplet integration vehicles needs to be explored, and the induced stress needs to be managed to improve longterm reliability. ...
... The stress-induced failure in chiplet applications is costly and unbearable because the failure of a single die would cause failure of the monolithic chip [30], but current studies are focused on the warpage behavior investigation of multi-chiplet systems [32,37]. Accordingly, the stress generation mechanism during fabrication of chiplet integration vehicles needs to be explored, and the induced stress needs to be managed to improve long-term reliability. ...
The multi-chiplet technique is expected to be a promising solution to achieve high-density system integration with low power consumption and high usage ratio. This technique can be integrated with a glass interposer to accomplish a competitive low fabrication cost compared with the silicon-based interposer architecture. In this study, process-oriented stress simulation is performed by the element activation and deactivation technique in finite element analysis architecture. The submodeling technique is also utilized to mostly conquer the scale mismatch and difficulty in mesh gridding design. It is also used to analyze the thermomechanical responses of glass interposers with chiplet arrangements and capped epoxy molding compounds (EMC) during curing. A three-factor, three-level full factorial design is applied using the analysis of variance method to explore the significance of various structural design parameters for stress generation. Analytic results reveal that the maximum first principal stresses of 130.75 and 17.18 MPa are introduced on the sidewall of Cu-filled via and the bottom of the glass interposer, respectively. Moreover, the EMC thickness and through glass via pitch are the dominant factors in the adopted vehicle. They significantly influence the stress magnitude during heating and cooling.
... With the development of semiconductor manufacturing processes, Chiplet-based systems have been widely investigated to achieve the continuation of Moore's law [1][2][3]. Due to the advantages of miniaturization, high performance, and low cost, Chiplet-based systems have been applied in computing systems and processing-in-memory systems [4][5][6]. Through silicon via (TSV) is a key technology to achieve vertical interconnection between different dies in Chiplet-based systems [7][8][9][10][11]. In order to satisfy the requirements of various applications, cylindrical, tapered, and coaxial TSVs (CTSVs) have been proposed [12][13][14]. ...
In this research, an efficient thermal-stress coupling design method for a Chiplet-based system with a coaxial through silicon via (CTSV) array is developed by combining the support vector machine (SVM) model and particle swarm optimization algorithm with linear decreasing inertia weight (PSO-LDIW). The complex and irregular relationship between the structural parameters and critical indexes is analyzed by finite element simulation. According to the simulation data, the SVM model is adopted to characterize the relationship between structural parameters and critical indexes of the CTSV array. Based on the desired critical indexes of the CTSV array, the multi-objective evaluation function is established. Afterwards, the structural parameters of the CTSV array are optimized through the PSO-LDIW algorithm. Finally, the effectiveness of the developed method is verified by the finite element simulation. The simulated peak temperature, peak stress of the Chiplet-based system, and peak stress of the copper column (306.16 K, 28.48 MPa, and 25.76 MPa) well agree with the desired targets (310 K, 30 MPa, and 25 MPa). Therefore, the developed thermal-stress coupling design method can effectively design CTSV arrays for manufacturing high-performance interconnect structures applied in Chiplet-based systems.
... The fact that nanoparticles have a melting point depression has opened up the possibilities of their new uses for the purposes of producing catalysts, semiconductors, sensors, etc. [17,18]. Conductive nanoparticles with a melting point depression have potential for use in smart devices [19][20][21][22], that can be implanted into the human body noninvasively. ...
A coupled process of ultrasonic spray pyrolysis and lyophilisation was used for the synthesis of dried gold nanoparticles. Two methods were applied for determining their melting temperature: uniaxial microcompression and differential scanning calorimetry (DSC) analysis. Uniaxial microcompression resulted in sintering of the dried gold nanoparticles at room temperature with an activation energy of 26–32.5 J/g, which made it impossible to evaluate their melting point. Using DSC, the melting point of the dried gold nanoparticles was measured to be around 1064.3°C, which is close to pure gold. The reason for the absence of a melting point depression in dried gold nanoparticles was their exothermic sintering between 712 and 908.1°C.
... With the projected widespread adoption of HI systems, the cost of packaging is projected to dominate design [33]. Although there are several sustainability reports from large semiconductor manufacturing and design companies, these reports do not specifically break down the contributions from packaging. ...
Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an increase in embodied emissions, encompassing carbon emissions arising from design, manufacturing, packaging, and other infrastructural activities. While existing research has developed tools to analyze embodied carbon at the computer architecture level for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: ``reducing" computation by reusing pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. The reuse of chiplets across multiple designs, even spanning multiple generations of integrated circuits (ICs), can substantially reduce embodied carbon emissions throughout the operational lifespan. This paper introduces a carbon analysis tool specifically designed to assess the potential of HI systems in facilitating greener VLSI system design and manufacturing approaches. The tool takes into account scaling, chiplet and packaging yields, design complexity, and even carbon overheads associated with advanced packaging techniques employed in heterogeneous systems. Experimental results demonstrate that HI can achieve a reduction of embodied carbon emissions up to 70\% compared to traditional large monolithic systems. These findings suggest that HI can pave the way for sustainable computing practices, contributing to a more environmentally conscious semiconductor industry.
... El nivel de inversión para la producción de semiconductores es alta debido a los altos costos de producción, por ejemplo, el costo del diseño de chips semiconductores de 7 nm está alrededor de 300 millones de dólares y en los chips semiconductores de 3 nm se espera que incremente 5 veces el nivel de costo ahondando en 1.5 billones de dólares anglosajones (Li, et al., 2020). ...
... In 2.5-D IC, a system on chip (SoC) is separated into numerous functional blocks, known as chiplets, which are placed side-by-side on the interposer and coupled with high speed and bandwidth through the interposer [6]; 2.5-D integration significantly reduces the design cycle, complexity, and expense, and it supports the reuse of off-the-shelf intellectual properties (IPs) and the heterogeneity of blocks across many technologies [7]. SoC designers can only replace the part of the chiplets according to the requirement rather than redesign the entire system [8]. Additionally, the development risk of SoC in 2.5-D integration is significantly lower than that of a conventional 2-D IC design as a result of the known good dies [9] being selected as chiplets. ...
A chiplet multi-objective optimization algorithm for 2.5-D integrated circuit (IC) based on a passive interposer is discussed in this article. Inspired by the network-on-chip mapping problem, we propose a novel algorithm, called chiplet multi-objective optimization, which minimizes the average temperature and the communication consumption between chiplets at the same time. The algorithm considers the specificities of 2.5-D IC chiplets, such as the spacing and different sizes of chiplets. In addition to the weight factor, α is also introduced to make a balance between temperature and the communication consumption. The designer can change the weight factor according to their own requirement. The multi-window display system is used as an example in this article to demonstrate the algorithm’s efficiency and the accuracy. According to our algorithm, the system temperature of the most ideal solution can be reduced by 8.34 K and the communication consumption reduced by 232.13 μJ.
