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Cyclic Redundancy Check (CRC) is an essential component in various integrated circuits of the electronics industry. This paper is a CRC comprehensive guide that explores various approaches for CRC implementations in hardware, and demonstrates synthesis estimation results for understanding their impact. Finally, it assists the designer to customize...
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Context 1
... the multiplexer and shifter with H matrices: In order to reduce the critical path by removing the shifter and multiplexer that pre-pends the CRC to the last sub-message as mentioned in Section III-C1, it might seem reasonable to create a Func B that encompasses the whole task of evaluating the next cycle CRC. If we assume that the granularity of the datapath is double words, then there will be a need for 4 H matrix multiplication functions: H 32 , H 64 , H 96 , H 128 as shown in Figure 5(a). While processing sub-messages other than the last sub-message, H 128 will be used. ...
Context 2
... it be noted that two H 32 circuits can be cascaded vertically to generate a slower and larger H 64 . This can be taken advantage of if the path in Func A is the critical one, and there is some positive slack in Func B. Then there would be margin to implement a slightly more area optimized Func B as shown in Figure 5(b). Four H 32 are used to generate any of the four H functions H 32 , H 64 , H 96 , H 128 . ...
Context 3
... results in smaller area, but greater longest path. Our findings demonstrate that by adopting the design in Figure 5(b) instead of the one in Figure 5(a), the area of Func B would be decreased by 6.13% on the expense of an increase in delay that is as low as 0.73%. In summary, we still cannot depend on the advanced RTL programming capabilities of Verilog and VHDL due to the fact that the results are strongly dependent on the synthesis tool. ...
Context 4
... results in smaller area, but greater longest path. Our findings demonstrate that by adopting the design in Figure 5(b) instead of the one in Figure 5(a), the area of Func B would be decreased by 6.13% on the expense of an increase in delay that is as low as 0.73%. In summary, we still cannot depend on the advanced RTL programming capabilities of Verilog and VHDL due to the fact that the results are strongly dependent on the synthesis tool. ...
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Citations
... FFT [39] is represented with pseudocode in Algorithm 1, where FFT128 and FFT32 refer to a sample size of 128 and 32, respectively. CRC32 [40] that generates 32-bit hash value is represented with pseudocode in Algorithm 2. Produced 32-bit hash is often used as a checksum to verify the integrity of data. MD5 [41], a widely-used cryptographic hash function that produces a 128-bit (16-byte) hash value is represented in Algorithm 3. SHA-256 [42], a cryptographic hash function that generates a 256-bit (32-byte) hash value is represented in Algorithm 4. This algorithm takes input data of any length and produces a unique, fixed-length 256-bit hash. ...
Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%.
