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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-preci...
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In this study, a novel binary parallel multiplier circuit was designed and implemented. The proposed multiplier is a combination of two separate circuits, namely a truncated multiplier circuit and a least significant bit (LSB) circuit. The LSB multiplier was designed based on a Vedic mathematical expression, but some modifications were made to matc...
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... Research on the application of Vedic mathematics in quantum-dot cellular automata (QCA) circuits has been an active area of research in recent years. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic sutra [7]. ...
... 7 We observe that the work done in references 8-11 has structures with Coplanar orientation. Our results show that the FoM i.e. the Quantum Cost has the least value of 0.27 in our structure. ...
Advantages like working at high speed, scalability, and lower power consumption make QCA technology more feasible than modern CMOS technology. QCA Technology uses electrons’ Coulombic interaction and polarization to represent binary information 0 and 1. The present paper proposes a novel XOR Gate and a Half Adder design and uses them to implement a new 2x2 Vedic Multiplier on QCA technology. A 2x2 Vedic Multiplier multiplies two inputs, of two bits each, using Urdhva-Tiryakbhyam Vedic Sutra. The proposed circuit has a reduced cell count and Quantum cost compared Co-planar Vedic Multipliers to available in the literature. QCADesigner 2.0.3 is used for the simulation and verification of all three proposed circuits.
... Finally, adjust the output sign according to the sign of the inputs. This methodology is explained and designed in traditional logic in previous research [2]. ...
... The generation of product terms is similar to the product terms generation in the array multiplier. The difference is that the product terms are added concurrently instead of generating partial products and adding them by n-bit binary adders [2]. ...
... The second technique is used in [2]. The advantage of this technique is that Vedic Multiplier can be expanded for the required number of input digits, then use the appropriate 2's complement circuit and a mux to select between the signed/unsigned and positive/negative numbers. ...
One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two's complement (B2C) and MUX circuits, while DesignII combines binary two's complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.
... Recently, digital sub threshold circuit design has turned out to be a very promising method for ultralow power applications [3][4]. The adder is one of the most critical mechanisms of a processor, as it is used in the arithmetic logic unit (ALU), in the floating-point unit, and for address generation in case of cache or memory access [5][6]. A dominant component of power consumption in today's VLSI circuits is leakage power when to operate the circuit in ultra sub threshold region [7]. ...
This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs.
... Pass transistor based MOS Switch Integrated Ultra Low Power 1-bit full adder (MOSSI-ULP) is the design by Vijayakumar and Reeba Korah for which the biasing techniques are applied to restore the full swing [8]. [11][12][13][14][15][16]. From the literature it has been clear that power and delay are the two performance metrics which can decide the energy metric of a digital circuit in low power applications. ...
This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.
... Power and delay are the two performance metrics which comprehensively decide the energy metric of the system in low power application and high performance computing in IoT applications. [4][5]. ...
In this paper, two performance metrics power and delay are estimated for various XOR-XNOR circuits and Multiplexer for designing 4-2 compressor. The main objective is to design an energy efficient compressor for computing applications in FIR filter. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 4-2 compressors consist of six blocks out of which two XOR-XNOR blocks and four MUX blocks. The average power, delay and energy consumed by the proposed compressor which is based on 5T XOR-XNOR and GDIMUX design is 85.72 nW, 62.53 pS and 5.36 aJ respectively
