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![Figure 4. Generalized Structure for Fault Tolerant Full Adder [12]](profile/M-Venkatesha/publication/249316170/figure/fig4/AS:297364481953806@1447908625503/Generalized-Structure-for-Fault-Tolerant-Full-Adder-12_Q320.jpg)
Reversible Logic is gaining significant consideration as the potential logic
design style for implementation in modern nanotechnology and quantum computing
with minimal impact on physical entropy .Fault Tolerant reversible logic is one
class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have be...
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Reversible logic is a computational model where all gates are logically reversible and combined in circuits such that no values are lost or duplicated. This paper presents a novel functional language that is designed to describe only reversible logic circuits. The language includes high-level constructs such as conditionals and a let-in statement t...
Citations
... It provides count for fundamental circuits used to develop any quantum logic circuits. Quantum cost for these reversible quantum gates will be '0' and '1' respectively [15] [16]. If the quantum cost of any designed digital circuits goes up then the efficiency comes down. ...
... Many other researchers have obtained good results in ALU optimization [8,9]. Saligram et al., [10] have proposed two faults tolerant ALU architectures but quantum cost of both circuits is unspecified. Bashiri and Haghparast [11] proposed fault tolerant ALU architecture but garbage and ancillary lines remain unoptimized as compare to number of operations performed. ...
... In an irreversible door, the sources of information and yields cannot be decided. The irreversible doors disseminate kTln2J, suggested by Landauer represents the warmth vitality of data lost and in which Boltzmann constant is represented by k, supreme temperature by T, where the circuit operation is taking place [1]. However, to overcome this cannot complete the scatter if the calculations are made by using the reversible way as demonstrated by Bennet [2]. ...
... This Vedic multiplier will be helpful for smart and massive calculations in processors. Another effort in the area of fault tolerant design was proposed using "parity preserving reversible logic gates" [7]. Bashiri and Haghparast [8] proposed parity preserving reversible ALU using 22 gates. ...
The birth to IC technology by Moore became driving force behind civilization and it spent almost 45 years successfully without any scruple in mind. It affected life of a mankind and brought pivotal moment in civilization. Now technology is hitting atomic levels and soon limits will be touched. Therefore time has come to rethink for an alternative solution that may slow down exponential rate demonstrated by Moore. Reversible computing is emerging as a superior technology and soon will be future of all smart computing applications. Although renowned physicists and computer scientists have investigated remarkable results in reversible logic based arithmetic logic unit (ALU) designing still research in the field of reversible ALU with add on fault tolerance is under progress and there is scope of further optimization. This paper aims in investigation of improved fault tolerant ALU architecture using parity preserving fault tolerant reversible adder (FTRA), double Feynman and conservative Fredkin gates. Performance evaluation of proposed architecture is done in respect of functionality, garbage lines, ancillary lines, quantum cost and number of gates. The quantum cost of all gates is verified using RCViewer+ tool. The proposed architecture is coded in Verilog HDL, Synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2.
... Parity checking is one of the methods for error detection in digital logic system. In parity preserving reversible circuit, parity preserving reversible logic gates [4] are used in which parity if input vector must match parity of output vector. A reversible circuit will be parity preserving if its individual gate is parity preserving. ...
... Besides the work on testing and test pattern generation (see, e. g., [21], [22], [23]), this also triggered the design of fault-detecting or fault-tolerant circuits -leading to the development of fault-tolerant libraries (see, e. g., [24], [25]) and corresponding design methods. The later includes the design of parity preserving reversible circuits which gained significant attention in the recent years and yielded several contributions such as [26], [27], [28], [29], [28], [30], [31], [32]. This development was motivated by the benefits of parity preservation in conventional circuits and aimed for adapting this to reversible circuits as well (this is discussed in more detail later in Section III). ...
... • In 2010, design of a full adder [29] using the building blocks from [28]. • In 2013, design of an ALU [30]. • In 2014, design a compressor [31]. ...
... Moreover, just fault tolerance is not sufficient without incorporating the fault recovery techniques also inside the design, for making it completely reliable and less error prone. Microprocessors are the most critical, important and necessary part of any modern digital systems and the heart of microprocessor is ALU [1]. If the ALU itself got faulty, the entire device will come to halt. ...
A new design for fault tolerant and fault recoverable ALU System has been proposed in this paper.
Reliability is one of the most critical factors that have to be considered during the designing phase of any
IC. In critical applications like Medical equipment & Military applications this reliability factor plays a
very critical role in determining the acceptance of product. Insertion of special modules in the main design
for reliability enhancement will give considerable amount of area & power penalty. So, a novel approach
to this problem is to find ways for reusing the already available components in digital system in efficient
way to implement recoverable methodologies. Triple Modular Redundancy (TMR) has traditionally used
for protecting digital logic from the SEUs (single event upset) by triplicating the critical components of the
system to give fault tolerance to system. ScTMR- Scan chain-based error recovery TMR technique provides
recovery for all internal faults. ScTMR uses a roll-forward approach and employs the scan chain
implemented in the circuits for testability purposes to recover the system to fault-free state. The proposed
design will incorporate a ScTMR controller over TMR system of ALU and will make the system fault
tolerant and fault recoverable. Hence, proposed design will be more efficient & reliable to use in critical
applications, than any other design present till today.
... Traditional computers are measured by bit unit and quantum computers are based on qubit or quantum bit unit [6]. Reversible logic is also a core part of the quantum circuit model [7]. ...
... The parity preserving property enables a quantum circuit for concurrent detection of permanent and transient faults by comparing the parity of its inputs and outputs [12]. Reversible logic is also a core part of the quantum circuit model [7]. The advantage of the method is in its implementation at the gate level. ...
Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.
... ALU needs to continually perform during the life-time of any computational devices such as a computer or a hand held device such as hand phone. Thus, reversible logic can be implemented in designing ALU to reduce the power dissipation and propagation delay in the circuits [8]. ...
In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.
... The idea is to design the reversible circuit in such a way that the parity between the input and the output bits are automatically conserved in absence of any error. After [16], there has been a series of sporadic works in this area, such as designing adders [9], divider [4], multiplier [17], multiplexer [19], ALU [20] etc. However, all of these designs are ad hoc, based on some pre-defined parity preserving reversible gates as building blocks. ...
Making a reversible circuit fault-tolerant is much more difficult than
classical circuit and there have been only a few works in the area of
parity-preserving reversible logic design. Moreover, all of these designs are
ad hoc, based on some pre-defined parity preserving reversible gates as
building blocks. In this paper, we for the first time propose a novel and
systematic approach towards parity preserving reversible circuits design. We
provide some related theoretical results and give two algorithms, one from
reversible specification to parity preserving reversible specification and
another from irreversible specification to parity preserving reversible
specification. We also evaluate the effectiveness of our approach by extensive
experimental results.
