Soonhak Kwon

Publications (45)17.33 Total impact

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  Available from: dsp.taegu.ac.kr

  Chapter: Efficient Exponentiation for a Class of Finite Fields GF(2n) Determined by Gauss Periods

  Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong
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  ABSTRACT: We present a fast and compact hardware architecture of exponentiation in a finite field GF(2 n ) determined by a Gauss period of type (n,k) with k ≥ 2. Our construction is based on the ideas of Gao et al. and on the computational evidence that a Gauss period of type (n,k) over GF(2) is very often primitive when k ≥ 2. Also in the case of a Gauss period of type (n,1), i.e. a type I optimal normal element, we find a primitive element in GF(2 n ) which is a sparse polynomial of a type I optimal normal element and we propose a fast exponentiation algorithm which is applicable for both software and hardware purposes. We give an explicit hardware design using the algorithm. KeywordsFinite field–Gauss period–primitive element–exponentiation–optimal normal basis
  01/1970: pages 228-242;
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  Available from: daegu.ac.kr

  Article: A Bit Parallel Systolic Multiplier Over GF (2m) Using an Irreducible All One Polynomial

  Soonhak Kwon, Hoon Chang, Kim, Chun Pyo Hong
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  ABSTRACT: We present an improved design of a low complexity and a low latency bit parallel systolic multiplier over GF (2 m) when there is an irreducible all one polynomial (AOP) of degree m. It is shown that our multiplier has a latency m/2 + 1 and the number of latches in our basic cell is 5 with m(m + 1)/2 basic cells. On the other hand, previously known bit parallel systolic multiplier with an AOP polynomial has latency m + 1 and the number of latches in each basic cell is 3 with (m + 1) 2 basic cells. Consequently the latency and the hardware complexity of our multiplier are reduced by 50 percent and 17 percent, respectively, from a known multiplier. Therefore our multiplier provides a fast and a hardware efficient architecture for a bit parallel multiplication in GF (2 m).
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  Available from: dsp.daegu.ac.kr

  Article: FPGA implementation of high performance elliptic curve cryptographic processor over GF(2163)

  Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong
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  ABSTRACT: In this paper, we propose a high performance elliptic curve cryptographic processor over GF(2163), one of the five binary fields recommended by National Institute of Standards and Technology (NIST) for Elliptic Curve Digital Signature Algorithm (ECDSA). The proposed architecture is based on the López–Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for GF(2163) field arithmetic. To achieve high throughput rates, we design two new word-level arithmetic units over GF(2163) and derive parallelized elliptic curve point doubling and point addition algorithms with uniform addressing based on the López–Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143 MHz. Our design is roughly 4.8 times faster with two times increased hardware complexity compared with the previous hardware implementation proposed by Shu et al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.
  Journal of Systems Architecture.
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  Available from: taegu.ac.kr

  Article: Novel Arithmetic Unit in GF (2 m) for Reconfigurable Hardware

  Hoon Chang, Kim, Soonhak Kwon, Jong Jin Kim, Chun Pyo Hong
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  ABSTRACT: In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this paper proposes a novel arithmetic unit (AU) in GF(2 m) for modern field programmable gate arrays (FPGAs). The proposed novel AU can perform both division and multiplication in GF(2 m). In other word, when input data come in continuously, it can produce division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that the hardware complexity of the proposed AU is significantly less than the previously proposed related circuit with lower maximum cell delay time and latency. Furthermore, since there are no global signals broadcasting in our design, the proposed architecture achieves a high clock rate for large field size m. Therefore, the proposed novel AU is well suited for both division and multiplication circuit of ECC implemented on FPGAs.
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  Available from: dsp.daegu.ac.kr

  Article: More efficient systolic arrays for multiplication in GF(2m) using LSB first algorithm with irreducible polynomials and trinomials

  Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong
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  ABSTRACT: Systolic arrays for multiplication in GF(2m) of Yeh et al. with LSB (least significant bit) first algorithm have the unfavorable properties such as increased area complexity and bidirectional data flows compared with the arrays of Wang and Lin with MSB (most significant bit) first algorithm. In this paper, by using a polynomial basis with LSB first algorithm, we present new bit parallel and bit serial systolic arrays over GF(2m). Our bit parallel systolic multiplier has unidirectional data flows with seven latches in each basic cell. Also our bit serial systolic array has only one control signal with eight latches in each basic cell. Thus our new arrays with LSB first algorithm have shorter critical path delay, comparable hardware complexity, and have the same unidirectional data flows compared with the arrays using MSB first algorithm. We also present new linear systolic arrays for multiplication in GF(2m) using irreducible trinomial xm+xk+1. It is shown that our linear arrays with trinomial basis have reduced hardware complexity since they require two fewer latches than the linear systolic arrays using general irreducible polynomials.
  Computers & Electrical Engineering.