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Multiple-Valued Logic and Soft Computing. 01/2012; 18:99-114.
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40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 26-28 May 2010; 01/2010
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ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan; 01/2009
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Multiple-Valued Logic and Soft Computing. 01/2009; 15:361-377.
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ABSTRACT: Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.
10/2008;
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2008; 27:436-444.
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38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA; 01/2008
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Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008; 01/2008
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ABSTRACT: This paper considers variable reordering for quantum multiple-valued decision diagrams (QMDD) used to represent the matrices describing reversible and quantum gates and circuits. An efficient method for adjacent variable interchange is presented and this method is employed to implement sifting of QMDDs. Experimental results are presented showing the effectiveness of the proposed techniques.
Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on; 06/2007
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IET Computers & Digital Techniques. 01/2007; 1:98-104.
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01/2007; Morgan & Claypool Publishers.
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ACM Trans. Design Autom. Electr. Syst. 01/2007; 12.
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ABSTRACT: This paper investigates two approaches for Boolean matching using NPN equivalence matching. Luks' hypergraph method is implemented and compared to the Walsh spectral decision diagram (SDD) method that we propose here. Both methods determine a canonical representation for each NPN equivalence class. The target functions are then transformed into a canonical representation and compared to the representative canonical forms for the NPN classes. This paper presents the implementation and results of the spectral method in detail. It is shown that the spectral method compares favorably to Luks' method and is better in terms of computational requirements for large functions
Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on; 11/2006
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ABSTRACT: A breadth-first search method for determining optimal 3-line circuits composed of quantum NOT, CNOT, controlled-V and controlled-V+ (NCV) gates is introduced. Results are presented for simple gate count and for technology motivated cost metrics. The optimal NCV circuits are also compared to NCV circuits derived from optimal NOT, CNOT and Toffoli (NCT) gate circuits. The work presented here provides basic results and motivation for continued study of the direct synthesis of NCV circuits, and establishes relations between function realizations in different circuit cost metrics.
12/2005;
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2005; 24:807-817.
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2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany; 01/2005
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IEEE Trans. VLSI Syst. 01/2005; 13:765-769.
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34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada; 01/2004
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2003 International Conference on Computer-Aided Design (ICCAD'03), November 9-13, 2003, San Jose, CA, USA; 01/2003
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Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003; 01/2003