D. Michael Miller

University of Victoria, Victoria, British Columbia, Canada

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Publications (38)6.1 Total impact

  • Zahra Sasanian, Robert Wille, D. Michael Miller
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    ABSTRACT: In previous work and motivated by a theoretical discussion on physical realizations, a new quantum gate library (the NCV-v1 library) for electronic design automation of quantum circuits has been proposed. Here, qudits instead of qubits are assumed, i.e. a basic building block which does not rely on a two level quantum system but a (multiple-valued) d-level quantum system is assumed. However, the descriptions on the foundation of this new library remained brief. This technical report provides an extended description of the applied ideas and concepts.
    09/2013;
  • Mathias Soeken, D. Michael Miller, Rolf Drechsler
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    ABSTRACT: The Pauli matrices are a set of three 2x2 complex Hermitian, unitary matrices. In this article, we investigate the relationships between certain roots of the Pauli matrices and how gates implementing those roots are used in quantum circuits. Techniques for simplifying such circuits are given. In particular, we show how those techniques can be used to find a circuit of Clifford+T gates starting from a circuit composed of gates from the well studied NCV library.
    Physical Review A 08/2013; 88(4). · 3.04 Impact Factor
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    ABSTRACT: Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large. In this paper, the relation between the gate costs of a reversible circuit and the number of circuit lines is considered. We observe that by slightly increasing the number of circuit lines, significant reductions in the gate cost can be obtained. Vice versa, by accepting a small increase in the gate costs, the number of lines can significantly be reduced. Following these observations, two optimization approaches are applied to demonstrate and experimentally evaluate these effects. The optimization approaches generate alternative circuit realizations from which the best one can be picked with regard to the designers' requirements. As a result, a synthesis scheme is proposed that does not focus on a single cost metric, but trades off the competing requirements.
    Integration the VLSI Journal 01/2013; · 0.41 Impact Factor
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    Zahra Sasanian, Robert Wille, D. Michael Miller
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    ABSTRACT: Quantum computing offers a promising alternative to conventional computation due to the theoretical capacity to solve many important problems with exponentially less complexity. Since every quantum operation is inherently reversible, the desired function is often realized in reversible logic and then mapped to quantum gates. We consider the realization of reversible circuits using a new class of quantum gates. Our method uses a mapping that grows at a very low linear rate with respect to the number of controls. Results show that, particularly for medium to large circuits, our method yields substantially smaller quantum gate counts than do prior approaches.
    01/2012;
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    ABSTRACT: This paper considers the optimization of reversible circuits composed of multiple-control Toffoli gates to quantum circuits using the well-known NCV-1 (NCV) library and the recently introduced NCV-v1 library which both use a four-valued model for the quantum gates. The techniques introduced handle positive and negative controls which are central to many reversible circuit synthesis procedures. Experimental results confirm the methods are applicable to circuits obtained by diverse synthesis methods. The results also show the significant advantage of the NCV-v1 library.
    Proceedings of The International Symposium on Multiple-Valued Logic 01/2012;
  • Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
    Multiple-Valued Logic and Soft Computing. 01/2012; 18:99-114.
  • Zahra Sasanian, D. Michael Miller
    Multiple-Valued Logic and Soft Computing. 01/2012; 18:83-98.
  • Zahra Sasanian, D. Michael Miller
    [show abstract] [hide abstract]
    ABSTRACT: Multiple-control Toffoli (MCT) gates are widely used in the synthesis of reversible circuits. These gates are not usually directly implemented and need to be mapped to circuits of more elementary components such as quantum gates. In this work, the realization of MCT gates with mixed controls is explored for the NCV quantum library containing NOT, CNOT, V and V + gates. The results show that the proposed approach significantly improves the best known NCV costs for MCT gates. 1
    01/2011;
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    D Michael Miller, Robert Wille, Z Sasanian
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    ABSTRACT: A new method for determining elementary quantum gate realizations for multiple-control Toffoli (MCT) gates is presented. The realization for each MCT gate is formed as a composition of realizations of smaller MCT gates. A marking algorithm which is more effective than the traditional moving rule is used to optimize the final circuit. The main improvement is that the resulting circuits make significantly better use of ancillary lines than has been achieved in earlier approaches. Initial results are also presented for circuits with nearest-neighbour communication. These results show that the overall approach is not as effective for that problem indicating that research on direct synthesis of nearest-neighbour quantum circuits should be considered. While, the results presented are for the NCV quantum gate library (i.e. for quantum circuits composed of NOT gates, controlled-NOT gates, and controlled-V /V + gates), the approach can be applied to other libraries of elementary quantum gates.
    Proceedings of The International Symposium on Multiple-Valued Logic 01/2011;
  • Source
    D. Michael Miller, Robert Wille, Rolf Drechsler
    [show abstract] [hide abstract]
    ABSTRACT: Additional lines are required to implement an irreversible function as a reversible circuit. The emphasis, particularly in automated synthesis methods, has been on using the minimal number of additional lines. In this paper, we show that circuit cost reductions can be achieved by adding additional lines. We present an algorithm for line addition that can be targeted to reducing the quantum cost of a circuit or the transistor count for a CMOS implementation. Experimental results show that the cost reduction can be significant even if (1) only a small number of lines (even one) is added and (2) other circuit optimizations have already been applied.
    40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 26-28 May 2010; 01/2010
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    ABSTRACT: Spectral techniques on Abelian groups are a well-established tool in diverse fields such as signal processing, switching theory, multi-valued logic and logic design. The harmonic analysis on finite non-Abelian groups is an extension of them, which has also found applications for particular tasks in the same fields. It takes advantages of the peculiar features of the domain groups and their dual objects. Representing unitary irreducible representations, that are kernels of Fourier transforms on non-Abelian groups, in a compact manner is a key task in this area. These representations are usually specified in terms of rectangular matrices with matrix entries. Therefore, the problem of their efficient representations can be viewed as handling large rectangular matrices with matrix-valued entries. Quantum Multiple-valued Decision Diagrams (QMDDs) and Heterogeneous Decision Diagrams (HDDs) have been used for representation of matrices with numerical values, under some restrictions to the order of matrices to be represented. In this paper, we present a generalization of this concept for the representation of rectangular matrices with matrix-valued entries. We also demonstrate an implementation of an XML-based software package aimed at handling such data structures.
    40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010, Barcelona, Spain, 26-28 May 2010; 01/2010
  • D. Michael Miller, Radomir S. Stankovic
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    ABSTRACT: This paper describes a decision diagram package for efficient computation with large matrices. The heterogeneous decision diagrams supported by the package do not require the selection variables to have a single domain. Computations can be over a selected field up to the complex numbers including finite fields. Implementation strategies supporting this level of flexibility are presented. Applications are outlined taken from diverse areas such as reversible and quantum logic, spectral transformations and operations over finite fields.
    Computer Aided Systems Theory - EUROCAST 2009, 12th International Conference, Las Palmas de Gran Canaria, Spain, February 15-20, 2009, Revised Selected Papers; 01/2009
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    ABSTRACT: This paper describes new metrics for size minimization of the data struc- ture referred to as quantum multiple-valued decision diagrams (QMDD). QMDD are used to represent the matrices describing reversible and quan- tum gates and circuits. We explore metrics related to the frequency of edges with non-zero weight for the entire QMDD data structure and their his- tograms with respect to each variable. We observe some unique regularity particular to the methodology of the QMDD. We develop new heuristics for QMDD dynamic variable ordering (DVO) that are guided by the proposed metrics. An exhaustive sifting procedure was implemented for benchmark circuits with up to ten variables to obtain the optimal minimization, demon- strating the effectiveness of the proposed minimization techniques based on data structure metrics.
    Multiple-Valued Logic and Soft Computing. 01/2009; 15:361-377.
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    ABSTRACT: Determining the equivalence of reversible circuits de- signed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates. The specifica- tion can include don't-cares arising from constant inputs, garbage outputs, and total or partial don't-cares in the un- derlying target function. The paper explores well-known techniques from irreversible equivalence checking and how they can be applied in the domain of reversible circuits. Two approaches are considered. The first employs decision dia- gram techniques and the second uses Boolean satisfiability. Experimental results show that for both methods, circuits with up to 27,000 gates, as well as adders with more than 100 inputs and outputs, are handled in under three minutes with reasonable memory requirements.
    ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan; 01/2009
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    Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
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    ABSTRACT: Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.
    10/2008;
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    ABSTRACT: This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.
    Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008; 01/2008
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    D. Michael Miller, Mitchell Aaron Thornton
    01/2008; Morgan & Claypool Publishers., ISBN: 978-1-59829-190-2
  • IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2008; 27:436-444.
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    ABSTRACT: This paper investigates two approaches for Boolean matching using NPN equivalence matching. Luks' hypergraph method is implemented and compared to the Walsh spectral decision diagram (SDD) method that we propose here. Both methods determine a canonical representation for each NPN equivalence class. The target functions are then transformed into a canonical representation and compared to the representative canonical forms for the NPN classes. This paper presents the implementation and results of the spectral method in detail. It is shown that the spectral method compares favorably to Luks' method and is better in terms of computational requirements for large functions
    Design, Applications, Integration and Software, 2006 IEEE Dallas/CAS Workshop on; 11/2006
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    Dmitri Maslov, D. Michael Miller
    [show abstract] [hide abstract]
    ABSTRACT: A breadth-first search method for determining optimal 3-line circuits composed of quantum NOT, CNOT, controlled-V and controlled-V+ (NCV) gates is introduced. Results are presented for simple gate count and for technology motivated cost metrics. The optimal NCV circuits are also compared to NCV circuits derived from optimal NOT, CNOT and Toffoli (NCT) gate circuits. The work presented here provides basic results and motivation for continued study of the direct synthesis of NCV circuits, and establishes relations between function realizations in different circuit cost metrics.
    12/2005;

Publication Stats

394 Citations
17 Downloads
1k Views
6.10 Total Impact Points

Institutions

  • 1995–2013
    • University of Victoria
      • Department of Computer Science
      Victoria, British Columbia, Canada
  • 2006
    • Southern Methodist University
      • Department of Computer Science and Engineering
      Dallas, TX, United States
  • 2004–2005
    • University of New Brunswick
      • Faculty of Computer Science
      Fredericton, New Brunswick, Canada
  • 2000
    • Stockholm Environment Institute
      Tukholma, Stockholm, Sweden