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C.-H. Jan,
P. Bai,
J. Choi,
G. Curello,
S. Jacobs,
J. Jeong,
K. Johnson,
D. Jones,
S. Klopcic,
J. Lin, [......],
G. Sacks,
B. Turkot,
Y. Wang,
L. Wei,
J. Yip,
I. Young,
K. Zhang,
Y. Zhang,
M. Bohr,
B. Holt
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ABSTRACT: A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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K. Kuhn,
M. Agostinelli,
S. Ahmed,
S. Chambers,
S. Cea,
S. Christensen,
P. Fischer,
J. Gong,
C. Kardas,
T. Letson, [......],
S.W. Pae,
I. Post,
S. Putna,
K. Raol, A. Roskowski,
R. Soman,
T. Thomas,
P. Vandervoorn,
M. Weiss,
I. Young
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ABSTRACT: This paper presents a highly-manufacturable process technology featuring SiGe HBT devices fully integrated into a 90 nm leading-edge high performance CMOS technology. The technology was developed on a 300 mm wafer platform, and supports process elements including RF CMOS devices, a MIM capacitor, precision resistors, high-Q inductors and varactors.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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S. Pae,
M. Agostinelli,
M. Brazier,
R. Chau,
G. Dewey,
T. Ghani,
M. Hattendorf,
J. Hicks,
J. Kavalieros,
K. Kuhn, [......],
M. Metz,
K. Mistry,
C. Prasad,
S. Ramey, A. Roskowski,
J. Sandford,
C. Thomas,
J. Thomas,
C. Wiegand,
J. Wiedemer
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ABSTRACT: In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
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C. Prasad,
M. Agostinelli,
C. Auth,
M. Brazier,
R. Chau,
G. Dewey,
T. Ghani,
M. Hattendorf,
J. Hicks,
J. Jopling, [......],
M. Metz,
K. Mistry,
S. Pae,
W. Rachmady,
S. Ramey, A. Roskowski,
J. Sandford,
C. Thomas,
C. Wiegand,
J. Wiedemer
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ABSTRACT: In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
