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B. Doris,
Y. Zhang,
D. Fried,
J. Beintner,
O. Dokumaci,
W. Natzle,
H. Zhu,
D. Boyd,
J. Holt,
J. Petrus,
J.T. Yates,
T. Dyer, P. Saunders,
M. Steen,
E. Nowak,
M. Ieong
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ABSTRACT: A new concept in high performance VLSI called Simplified Hybrid Orientation Technology (SHOT) is introduced. This novel process flow creates circuits with independently oriented surface channels for pMOS and nMOS by integrating FinFETs with planar Ultra-Thin SOI (UTSOI) MOSFETs for the first time. The unique CMOS structure enables high mobility surface channel orientation for both devices. The SHOT scheme is also capable of producing PDSOI devices on the same chip. pFinFET drive current is among the best results reported (810 μA/μm at V<sub>dd</sub> = 1.2V).
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: In strained Si/Si<sub>1-x</sub>Ge, NMOS, As dopant diffusivity was found to increase exponentially with %Ge and this becomes a significant roadblock for ultra-shallow As junction formation for high %Ge(>20%). A new approach which uses a co-implant to retard As motion has been developed and is applicable for a range of %Ge (20-75%) and Si cap (5-20 nm). For 20% Ge with 20 nm Si cap, it has created one of the shallowest and most abrupt N<sup>+</sup> junctions thus far; Xj∼20 nm & Xjs∼5 nm/dec. Importantly, junction activation is not affected by the new method. In addition, for As diffusion, the strain in the Si cap was found to have a minimal effect.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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K. Rim,
K. Chan,
L. Shi,
D. Boyd,
J. Ott,
N. Klymko,
F. Cardone,
L. Tai,
S. Koester,
M. Cobb,
D. Canaperi,
B. To,
E. Duch,
I. Babich,
R. Carruthers, P. Saunders,
G. Walker,
Y. Zhang,
M. Steen,
M. Ieong
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ABSTRACT: A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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ABSTRACT: The diffusion of implanted boron in strained Si/Si<sub>1-x</sub>Ge<sub>x</sub> is investigated. A continuum segregation model (CSM) is presented to describe the phenomenon of B pile-up into the germanium profile. An analytic formula is obtained for Ge pre-amorphization and a modified pre-amorphization model is used in TSUPREM4 in order to accurately model our measurement data. Our simulations of boron diffusion are in reasonable agreement with our SIMS data. Comparison of the CSM with the model of immobile boron-germanium clusters is also discussed.
Simulation of Semiconductor Processes and Devices, 2002. SISPAD 2002. International Conference on; 02/2002
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J. Kedzierski,
E. Nowak,
T. Kanarsky,
Y. Zhang,
D. Boyd,
R. Carruthers,
C. Cabral,
R. Amos,
C. Lavoie,
R. Roy, [......],
K. Wong,
D. Canaperi,
M. Krishnan,
K.-L. Lee,
B.A. Rainey,
D. Fried,
P. Cottrell,
H.-S.P. Wong,
M. Ieong,
W. Haensch
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ABSTRACT: Metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation. Devices satisfy the following metal-gate technology requirements: ideal mobility, low gate leakage, high transconductance, competitive I<sub>on</sub>/I<sub>off</sub>, and adjustable V<sub>t</sub>. Six silicide gate materials are presented, as well as two silicide workfunction engineering methods.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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ABSTRACT: For junction formation in strained Si on relaxed Si<sub>1-x</sub>Ge<sub>x</sub> substrates with x=15-30%, shallower and more abrupt boron P<sup>+</sup> extension junction is achieved as the %Ge in the relaxed Si<sub>1-x</sub>Ge<sub>x</sub> is increased. At x=30%, a factor of 2 improvement in both junction depth Xj and abruptness Xjs is achieved over that formed in bulk Si. Further reductions in Xj and Xjs were achieved by vacancy injection during RTA anneal with NH<sub>3</sub> ambient. However, this approach was found effective only for Ge concentration below 30% above which the boron diffusion mechanism apparently changes over from interstitial to vacancy. With 6 nm Si cap on 30% Si<sub>1-x</sub>Ge<sub>x</sub> layer, it creates one of the shallowest and most abrupt boron junctions yet achieved with RTA; Xj=23 nm and Xjs∼4.5 nm/dec. Better boron junction activation (>10%) is also achieved in strained Si/Si<sub>1-x</sub>Ge<sub>x</sub> layer than in bulk Si.
Electron Devices Meeting, 2002. IEDM '02. Digest. International; 02/2002
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J. Kedzierski,
D.M. Fried,
E.J. Nowak,
T. Kanarsky,
J.H. Rankin,
H. Hanafi,
W. Natzle,
D. Boyd,
Ying Zhang,
R.A. Roy, [......],
C.P. Willets,
A. Johnson,
S.P. Cole,
H.E. Young,
N. Carpenter,
D. Rakowski,
B.A. Rainey,
P.E. Cottrell,
M. Ieong,
H.-S.P. Wong
[show abstract]
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ABSTRACT: Double-gate FinFET devices with asymmetric and symmetric
polysilicon gates have been fabricated. Symmetric gate devices show
drain currents competitive with fully optimized bulk silicon
technologies. Asymmetric-gate devices show |V<sub>t</sub>|~0.1 V, with
off-currents less than 100 nA/um at V<sub>gs</sub>=0
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
