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ABSTRACT: We introduce on-demand redundancy, a set of architectural techniques that leverage the tightly-coupled nature of components in systems-on-chip to reduce the cost of safety-critical systems. On-demand redundancy eases the assumptions that traditionally segregate the execution of critical and non-critical tasks (NCTs), making resources available for critical tasks at potentially arbitrary points in both space and time, and otherwise freeing resources to execute non-critical tasks when critical tasks are not executing. Relaxed dedication is one such technique that allows non-critical tasks to execute on critical task resources. Our results demonstrate that for a wide variety of applications and architectures, relaxed dedication is more cost-effective than a traditional approach that employs dedicated resources executing in lockstep. Applied to dual-modular redundancy (DMR), relaxed dedication exposes 73% more NCT cycles than traditional DMR on average, across a wide variety of usage scenarios.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011; 04/2011
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ABSTRACT: Application-specific integrated circuits (ASICs) are physical implementations of algorithms, so implementation metrics are determined in large part by the algorithm specification. However, the system abstraction layers that have been developed to manage the ever-increasing complexity of digital systems separate algorithm designers from hardware designers, forcing the latter to work within the design space specified by the former, even for applications such as multimedia that do not have hard fidelity requirements. Designers typically employ informal iterative design to adjust fidelity, but a formal design methodology would increase designer efficiency and improve the quality of the solutions. This paper introduces such a methodology (and accompanying tool) that enables algorithm and implementation metrics to be co-optimized during early design exploration, opening the design space to include solutions that may provide, for example, significant performance improvements while only slightly compromising fidelity. Hierarchical dependency graphs (HDGs) are used to represent both the algorithm and the implementation architecture, providing a common interface through which algorithm designers and hardware designers can explore the collaborative space (ColSpace) together. Using the proposed technique, the ColSpace tool can trade off various metrics to find the best overall design while managing complexity with the HDG hierarchy. Two image processing case studies demonstrate that in ColSpace-optimized designs, latency savings can exceed fidelity losses, resulting in cost function reductions that would not have been possible without this co-optimization methodology.
Computer Design, 2009. ICCD 2009. IEEE International Conference on; 11/2009
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ABSTRACT: Hybrid FPGAs and structured ASICs make it possible to amortize nonrecurring engineering costs across multiple products, but such platforms have high area, performance, and power penalties. A new technique provides the flexibility to implement many product instances while maintaining the qualities of custom ASICs.
Computer 09/2009; · 1.47 Impact Factor
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ABSTRACT: Tremor, the most common form of movement disorder, is an often debilitating condition that adversely affects an individual's ability to maintain functional independence. Efforts to study, diagnose, and treat such movement disorders are complicated by a dearth of quantitative, precise, or accurate methods for motion data collection and assessment. To address this deficiency, this paper provides two contributions: 1) the design of a body-area inertial sensing system and 2) the evaluation of postcapture, on-body signal-processing algorithms that transform sensed inertial data into clinically significant information pertaining to tremor symmetry. For the former, we present our technology that meets requirements for wearability, fidelity, battery life, and interoperability. For the latter, we demonstrate the efficacy of using filter-bank analysis and cross correlation to interpret tremor frequency and energy. We extend the previous work by presenting a wireless body-area inertial sensing technology and a method to reduce, by up to 30 times, the computational demands of cross correlation on such a resource-constrained technology. These efforts lay the foundation for real-time, on-body assessment of tremor as well as more intelligent and energy-efficient data transmission and storage decisions.
IEEE Transactions on Biomedical Circuits and Systems 05/2009; · 2.03 Impact Factor
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ABSTRACT: Body area sensors can enable novel applications in and beyond healthcare, but research must address obstacles such as size, cost, compatibility, and perceived value before networks that use such sensors can become widespread.
Computer 02/2009; · 1.47 Impact Factor
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ABSTRACT: New attacker scenarios involving integrated circuits (ICs) are emerging that pose a tremendous threat to national security. Concerns about overseas fabrication facilities and the protection of deployed ICs have given rise to methods for IC authentication (ensuring that an IC being used in a system has not been altered, replaced, or spoofed) and hardware Trojan Horse (HTH) detection (ensuring that an IC fabricated in a nonsecure facility contains the desired functionality and nothing more), but significant additional work is required to quell these treats. This paper discusses how a technique for precisely measuring the combinational delay of an arbitrarily large number of register-to-register paths internal to the functional portion of the IC can be used to provide the desired authentication and design alteration (including HTH implantation) detection. This low-cost delay measurement technique does not affect the main IC functionality and can be performed at-speed at both test-time and run-time.
Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop on; 07/2008
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ABSTRACT: A number of applications depend on the protection of security-sensitive hardware, preventing unauthorized users from gaining access to the functionality of the integrated circuits (ICs). Failure to protect such devices can have consequences ranging from the loss of financial revenue to the loss of human lives. The key to providing protection does not lie in the prevention of theft but in a secure IC activation and user authentication procedure so that an adversary has nothing to gain by acquiring the physical hardware. The proposed protection scheme is robust against various types of malicious attack, such as reverse engineering to extract the circuit layout, brute-forcing the access key, and FIBing. The scheme provides the capability both for one-time or every-powerup activation and for every-powerup user authentication. Given the resource constraints of many security-sensitive hardware systems (such as those deployed in remote locations or carried in combat arenas), this paper proposes and evaluates the cost of several techniques for achieving secure activation and authentication.
Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop on; 07/2008
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ABSTRACT: Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs, which can often achieve better performance than CPUs on certain workloads. FPGAs are highly customizable, while GPUs provide massive parallel execution resources and high memory bandwidth. Applications typically exhibit vastly different performance characteristics depending on the accelerator. This is an inherent problem attributable to architectural design, middleware support and programming style of the target platform. For the best application-to-accelerator mapping, factors such as programmability, performance, programming cost and sources of overhead in the design flows must be all taken into consideration. In general, FPGAs provide the best expectation of performance, flexibility and low overhead, while GPUs tend to be easier to program and require less hardware resources. We present a performance study of three diverse applications - Gaussian elimination, data encryption standard (DES), and Needleman-Wunsch - on an FPGA, a GPU and a multicore CPU system. We perform a comparative study of application behavior on accelerators considering performance and code complexity. Based on our results, we present an application characteristic to accelerator platform mapping, which can aid developers in selecting an appropriate target architecture for their chosen application.
Application Specific Processors, 2008. SASP 2008. Symposium on; 07/2008
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ABSTRACT: TEMPO (Technology-Enabled Medical Precision Observation) 1.0 is a novel, first-generation, wearable data collection and analysis platform for assessment of a variety of human movement disorders, including tremor. It enables quantitative, objective, and continuous measurement of movement with minimal invasiveness and inconvenience to the patient and clinician, respectively. This system meets requirements for wearability, data storage, sampling rate, number of sensors, interface methods, and form factor, which are necessary for applications on person. In addition to the design and development of a basic data acquisition device, various circuits and systems were engineered to interface wearable, triaxial MEMS inertial sensors. Furthermore, custom data analysis software that processes datasets collected from the device and sensors, was created, and has demonstrated clinical utility in the analysis of tremor. Data processing techniques include a unique filtering scheme and a novel application of cross-correlation. The analysis was conducted pre- and post-operatively, in conjunction with the University of Virginia's Department of Neurosurgery, for a study of deep brain stimulation efficacy. This paper presents the engineering of and experimental results obtained with TEMPO 1.0 technology in the clinical assessment of tremor.
Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007. IEEE; 12/2007
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ABSTRACT: Essential tremor is the most common form of involuntary movement disorder and is often a debilitating condition for those affected. In the most severe cases, long-term suppression is achieved by chronic thalamic stimulation. This stimulation is defined with numerous parameters, and determining the optimal patient-specific settings requires accurate and precise assessment of tremor severity during programming. We introduce a technique to provide such assessment of essential tremor severity by applying the Teager energy function to data collected with TEMPO 1.0, a custom, wearable, inertial sensing technology for continuous, non-invasive, objective measurement of movement disorder such as tremor. This approach affords an opportunity to analyze tremor at a finer level of granularity than is currently possible with the clinical rating scale. Additionally, our technology facilitates further research of general tremor presentation, treatment, and etiology. Results obtained from a post-operative pilot study of deep brain stimulation efficacy at the University of Virginia's Department of Neurosurgery not only quantify tremor severity for programming enhancement, but also reveal axial tremor and ipsilateral benefit -both elusive tremor observations. This paper presents our approach and preliminary findings obtained from the clinical application of TEMPO 1.0.
Life Science Systems and Applications Workshop, 2007. LISA 2007. IEEE/NIH; 12/2007
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ABSTRACT: The increased process, voltage, and temperature (PVT) variability that comes with integrated circuit (IC) technology scaling has become a major problem in the semiconductor industry. In order to refine manufacturing processes and develop circuit design techniques to cope with variability, we must be able to accurately and precisely characterize the variations that occur. In this paper, we introduce a technique for characterizing combinational path delay variations by measuring a designer-controlled number of register-to-register delays in manufactured ICs with negative-skewed shadow registers. This technique enables delay measurements to be performed with at-speed tests that are run in parallel with and are orthogonal to other testing techniques, and therefore does not add combinatorial complexity to the testing process. This technique can be implemented cost-effectively on a large number of otherwise unobservable internal combinational paths to get accurate, precise data about delay variability.
Computer Design, 2007. ICCD 2007. 25th International Conference on; 11/2007
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ABSTRACT: Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, and presents a physics-based dynamic reliability model which returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. The model is verified with numerical simulations and reveals that blindly using the maximum temperature leads to too pessimistic lifetime estimation. Therefore, the proposed model not only increases the accuracy of reliability estimates, but also enables designers to reclaim design margin in reliability-aware design. In addition, the model is useful for improving the performance of temperature-aware runtime management by modeling system lifetime as a resource to be consumed at a stress-dependent rate
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2007; · 1.22 Impact Factor
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ABSTRACT: Wearable computing devices are becoming an important technology for medical diagnostic and treatment assessment. Many such devices have strict power and size requirements and are therefore often limited to small, integer- only signal processing microcontrollers. It is therefore a significant challenge to develop signal processing techniques that provide the necessary application fidelity with strict implementation limitations. One of our research projects involves the use of wearable devices to assess the efficacy of treatments for Essential Tremor and Parkinson's Disease patients. Accelerometers are used to measure the tremor, and the resultant signal spectra are analyzed using digital bandpass filters to measure the amount of tremor in each of several frequency bands. This paper presents a design procedure for integer-only filters (suitable for microcontroller implementation) using repeated convolution and frequency shifting that is shown to produce superior filters than those designed by commercial filter design tools.
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on; 12/2006
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ABSTRACT: Movement disorders affect millions of people and lead to increased rates of mortality and morbidity in the elderly population. To explore new treatments and facilitate preventative medicine, researchers are actively studying the epidemiology of movement disorder and employing technology to help expose its symptoms. A wearable device, TEMPO, developed at the University of Virginia, has enabled the collection of inertial data that accurately and precisely quantifies symptoms and physical manifestations of dysfunctional movement. To effectively leverage this data, however, flexible and extensible signal processing is necessary. This paper demonstrates the utility of the short-time Fourier transform and Haar discrete wavelet transform in the detection of transient episodes of freezing behavior and tripping in simulated gait datasets. Results show an improvement in exposing the anomalous events over existing frequency-domain measures.
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on; 12/2006
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ABSTRACT: Using a fixed temperature for thermal throttling is pessimistic. Reduced aging during periods of low temperature can compensate for accelerated aging during periods of high temperature. Runtime tracking of the temperature-dependent aging rate means that throttling is engaged only when necessary to maintain reliability. In this article, we show that the effect of cool (low-temperature) phases can compensate for that of hot (high-temperature) phases on reliability. Existing dynamic thermal management (DTM) techniques ignore the effects of temperature fluctuations on chip lifetime and can unnecessarily impose performance penalties for hot phases. Using electromigration as the targeted failure mechanism, we apply a dynamic reliability model and propose a dynamic reliability management (DRM) technique to dynamically track the consumption of chip lifetime during operation.
IEEE Micro 12/2005; 25(6):40- 49. · 1.78 Impact Factor
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ABSTRACT: FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher on-die temperatures and local hotspots. Sophisticated packaging techniques have become essential to maintain the health of the chip. In addition to static techniques to reduce the temperature, dynamic thermal management techniques are essential. Such techniques rely on accurate on-chip temperature information. In this paper, we present the design of a system that monitors the temperatures at various locations on the FPGA. This system is composed of a controller interfacing to an array of temperature sensors that are implemented on the FPGA fabric. Such a system can be used to implement dynamic thermal management techniques. We cross validate the sensor readings with values obtained from HotSpot, a pre-RTL architectural level thermal modeling tool.
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on; 11/2005
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ABSTRACT: Multi-mode systems have emerged as an area- and power-efficient approach to implementing multiple time-wise mutually exclusive algorithms and applications in a single hardware space. These systems have limited flexibility and temporal separation between modes is achieved by changing only the dataflow between components. This paper presents a synthesis methodology for integrating flexible components and controllers into primarily fixed logic multi-mode systems thereby increasing their overall flexibility and efficiency. The components are built using a technique called small-scale reconfigurability that provides the necessary flexibility without the penalties associated with general-purpose reconfigurable logic. The reconfiguration latency is small enabling both inter-mode and intra-mode reconfiguration of components. Datapath and controller area and power consumption are reduced beyond what is provided in current multi-mode systems using this methodology, without sacrificing performance. The results show an average 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and a 68% reduction in the number of controller signals for a set of benchmark 32-bit signal processing applications. There is also an average 38% increase in component utilization.
Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS '05. Third IEEE/ACM/IFIP International Conference on; 10/2005
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Reliability and Maintainability Symposium, 2005. Proceedings. Annual; 02/2005
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ABSTRACT: Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on; 12/2004
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ABSTRACT: A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been developed to help reduce leakage in SRAM-based memory, in which the percent leakage power is especially acute. SRAM-based field programmable gate arrays (FPGAs) pose similar leakage problems, but their structure and function require different solutions. This paper introduces a low complexity post-processing approach to reducing FPGA leakage current by ground-gating off SRAM cells that are unused in a particular device configuration. The approach is general enough to apply to any device configuration, and results reveal that the significant leakage current reduction can be achieved with no delay penalty and acceptable area overhead.
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on; 11/2004
